请大家帮忙看看这段VHDL哪里有问题？

只看该作者 · 2007-5-4 16:35

小弟是初学者，才写的1位全加器的代码，用MAX＋plus的，老是报这样的错：node'\mux21a:u2\:23.in1' missing source, 麻烦大家帮忙看看
，谢谢！
library ieee;
use ieee.std_logic_1164.all;
entity muxk is
port (a1,a2,a3,s0,s1: in std_logic;
               outy : out std_logic);
end entity muxk;
architecture a of muxk is
component mux21a
port ( a,b,s: in std_logic;
           y: out std_logic);
end component ;
signal tmp: std_logic;
begin
u1: mux21a port map ( a=>a2, b=>a3,s=>s0);
u2: mux21a port map ( a=>a1, b=>tmp, s=>s1,y=>outy);
end architecture a;

library ieee;
use ieee.std_logic_1164.all;
entity mux21a is
port(a,b : in  std_logic;
        s: in std_logic;
        y: out std_logic);
end mux21a ;
architecture b_mux21a of mux21a is
begin
  y<=(a and (not s)) or (b and s);
end b_mux21a;

library ieee;
use ieee.std_logic_1164.all;
entity mux21a is
port(a,b : in  std_logic;
        s: in std_logic;
        y: out std_logic);
end mux21a ;
architecture b_mux21a of mux21a is
begin
  process (a,b,s)
begin
if s='0' then y<=a;
else y<=b;
end if;
end process;
end b_mux21a;