|
library ieee;<br />use ieee.std_logic_1164.all;<br />entity Counter is<br />port(CLK: in std_logic;<br /> result: inout std_logic_vector(7 downto 0));<br />end entity;<br />architecture behavioral of Counter is<br />signal temp: std_logic_vector（7 downto 0);<br />begin<br /> process(CLK)<br /> begin<br /> if(CLK'event and CLK = '1') then temp <= temp + '1';--Error (10327): VHDL error at Counter.vhd(12): can't determine definition of operator ""+"" -- found 0 possible definitions<br /> end if;<br /> result <= temp;<br /> end process;<br />end behavioral; |
|
楼主
