library ieee;
use ieee.std_logic_1164.all;
entity Counter is
port(CLK: in std_logic;
result: inout std_logic_vector(7 downto 0));
end entity;
architecture behavioral of Counter is
signal temp: std_logic_vector（7 downto 0);
begin
process(CLK)
begin
if(CLK'event and CLK = '1') then temp <= temp + '1';--Error (10327): VHDL error at Counter.vhd(12): can't determine definition of operator ""+"" -- found 0 possible definitions
end if;
result <= temp;
end process;
end behavioral; |
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