各位朋友，帮忙看下下面的程序，看看那里需要修改，
报错提示如下：
Error (10818): Netlist error at JT.vhd(35): can't infer register for N[0] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for N[1] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for N[2] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for N[3] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for N[4] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for N[5] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for N[6] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for M[0] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for M[1] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for M[2] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for M[3] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for M[4] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for M[5] because it does not hold its value outside the clock edge
Error (10818): Netlist error at JT.vhd(35): can't infer register for M[6] because it does not hold its value outside the clock edge
Error (10822): HDL error at JT.vhd(35): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 16 errors, 8 warnings
Info: Allocated 132 megabytes of memory during processing
Error: Processing ended: Wed Jan 02 15:20:35 2008
Error: Elapsed time: 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 16 errors, 8 warnings
程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JT IS
PORT (CLK1: IN STD_LOGIC;
RST : IN STD_LOGIC;
JJ : IN STD_LOGIC;
EW : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
SN : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
T1 : IN INTEGER RANGE 0 TO 99;
T2 : IN INTEGER RANGE 0 TO 99;
T3 : IN INTEGER RANGE 0 TO 99;
Q1 : BUFFER INTEGER RANGE 0 TO 99;
Q2 : BUFFER INTEGER RANGE 0 TO 99 );
END ;
ARCHITECTURE kz OF JT IS
TYPE STATES IS (ST0,ST1,ST2,ST3);
SIGNAL current_state,next_state:states := st0 ;
SIGNAL M: INTEGER RANGE 0 TO 99 :=0;
SIGNAL N: INTEGER RANGE 0 TO 99 :=0;
BEGIN
COM: PROCESS(T1,T2,T3,CURRENT_STATE,RST,CLK1)
BEGIN
IF RST = '1' THEN NEXT_STATE <= ST0;
IF JJ = '1' THEN CURRENT_STATE<=CURRENT_STATE;M<=M;N<=N;
ELSE
CASE CURRENT_STATE IS
WHEN ST0 => EW <= "010";SN <= "100";M <= T1;N<=T2; NEXT_STATE <= ST1;
WHEN ST1 => EW <="001" ;SN <= "100";M <=T3;NEXT_STATE <= ST2;
WHEN ST2 => EW <="100" ;SN <= "010";M <=T2;N<=T1; NEXT_STATE <= ST3;
WHEN ST3 => EW <="100" ;SN <= "001";M <=T3; NEXT_STATE <= ST0;
END CASE;
END IF;END IF;
IF ( CLK1'EVENT AND CLK1='1') THEN M <=M-1;N <=N-1;END IF;
END PROCESS COM;
REG: PROCESS (JJ,CLK1,M,N)
BEGIN
Q1 <= M;Q2 <= N;
IF (M ="0" OR N ="0") THEN CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS REG;
END; |
楼主
标题置顶
标题高亮
