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-- mode?a¨|¨¨??¨oy?á??¨??a??¨oy??ê¨o??1¨o?¨|¨¨¨o?à??ê¨o?.|ì?à?a¨|¨¨¨o?à??ê¨o?¨o?à,inc?a????¨o?à????D?o?.p?a¨oy??1¨1????D?o?,N?a????¨oy??1¨1D?o?.<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.STD_LOGIC_ARITH.ALL;<br />use IEEE.STD_LOGIC_UNSIGNED.ALL;<br /><br />entity clock is<br /> Port ( N : out std_logic_vector(7 downto 0);<br /> P : out std_logic_vector(3 downto 0);<br /> clk : in std_logic;<br /> reset,mode,inc: in std_logic);<br />end clock;<br /><br />architecture Behavioral of clock is<br />SIGNAL divcounter,divcounter1: std_logic_vector(27 downto 0);<br />SIGNAL divclk,clk2:std_logic;<br />SIGNAL blink: std_logic_vector(3 downto 0);<br />SIGNAL scan:std_logic_vector(8 downto 0);<br />SIGNAL scan_clk:std_logic_vector(1 downto 0);<br />signal state:std_logic_vector(2 downto 0); --clock state.<br />SIGNAL sec_counter1,sec_counter2,min_counter1,min_counter2:std_logic_vector(3 downto 0);<br />--SIGNAL sec_counter1,sec_counter2,min_counter1,min_counter2:std_logic_vector(3 downto 0);<br />signal data:std_logic_vector(3 downto 0);<br /><br />begin<br />process(clk)<br />begin<br /> if clk='1' and clk'event then<br /> if(divcounter>=X"1312D00") then<br /> divcounter<=X"0000000";<br /> divclk<=not divclk;<br /> else <br /> divcounter<=divcounter+'1';<br /> end if;<br /> end if;<br /> end process;<br />--2Hz<br />process(clk)<br />begin<br /> if clk='1' and clk'event then<br /> if(divcounter1>=X"989680") then<br /> divcounter1<=X"0000000";<br /> clk2<=not clk2;<br /> else <br /> divcounter1<=divcounter1+'1';<br /> end if;<br /> end if;<br /> end process;<br /><br /><br />-- mode change<br />process(reset,divclk)<br />begin<br /> if(reset='0') then<br /> state<="000";<br /> elsif(divclk'event and divclk='1') then<br /> if(mode='0') then<br /> if(state>="100") then<br /> state<="000";<br /> else state<=state+'1';<br /> end if;<br /> end if;<br /> end if;<br />end process;<br /><br />process(state)<br />begin<br /> case state is<br /> when "000"=> blink<=(others=>'1');<br /> when "001"=> blink<=(0=>clk2,others=>'0');<br /> when "010"=> blink<=(1=>clk2,others=>'0');<br /> when "011"=> blink<=(2=>clk2,others=>'0');<br /> when "100"=> blink<=(3=>clk2,others=>'0');<br /> when others=><br /> end case;<br />end process;<br />--count<br />process(divclk,reset,state)<br />--variable sec_counter1,sec_counter2,min_counter1,min_counter2:std_logic_vector(3 downto 0);<br /> begin<br /> if(reset='0') then<br /> sec_counter1<=(others=>'0');<br /> sec_counter2<=(others=>'0');<br /> min_counter1<=(others=>'0');<br /> min_counter2<=(others=>'0');<br /> elsif (divclk'event and divclk='1') then<br /> case state is<br /> when "000"=><br /> if(sec_counter1>=X"9") then<br /> sec_counter1<=X"0";<br /> if(sec_counter2>=X"5")then<br /> sec_counter2<=X"0";<br /> if(min_counter1>=X"9")then<br /> min_counter1<=X"0";<br /> if(min_counter2>=X"5")then<br /> min_counter2<=X"0";<br /> else<br /> min_counter2<=min_counter2+'1';<br /> end if;<br /> else <br /> min_counter1<=min_counter1+'1';<br /> end if;<br /> else <br /> sec_counter2<=sec_counter2+'1';<br /> end if;<br /> else<br /> sec_counter1<=sec_counter1+'1';<br /> end if;<br /> when"001"=> <br /> if(inc='0') then<br /> if(min_counter2>=X"5")then<br /> min_counter2<=X"0";<br /> else min_counter2<=min_counter2+'1';<br /> end if;<br /> end if;<br /> when"010"=><br /> if(inc='0') then<br /> if(min_counter1>=X"9")then<br /> min_counter1<=X"0";<br /> else min_counter1<=min_counter1+'1';<br /> end if;<br /> end if;<br /> when"011"=><br /> if(inc='0') then<br /> if(sec_counter2>=X"5")then<br /> sec_counter2<=X"0";<br /> else sec_counter2<=sec_counter2+'1';<br /> end if;<br /> end if;<br /> when"100"=><br /> if(inc='0') then<br /> if(sec_counter1>=X"9")then<br /> sec_counter1<=X"0";<br /> else sec_counter1<=sec_counter1+'1';<br /> end if;<br /> end if;<br /> when others=> <br /> end case;<br /> end if;<br /> end process;<br /><br />--scan count<br />process(clk)<br /> begin<br /> if (clk'event and clk='1') then<br /> scan<=scan+1;<br /> end if;<br /> end process;<br /> scan_clk<=scan(8 downto 7);<br /><br />process(scan_clk)<br />begin<br /> case scan_clk is<br /> when "00"=><br /> data<=sec_counter1;<br /> P<="1000" and blink;<br /> when "01"=><br /> data<=sec_counter2;<br /> P<="0100" and blink; <br /> when "10"=><br /> data<=min_counter1;<br /> P<="0010" and blink; <br /> when "11"=><br /> data<=min_counter2;<br /> P<="0001" and blink;<br /> when others=>data<="1111";P<="0000";<br /> end case;<br />end process;<br /><br />process(data)<br />begin<br /> case data is<br /> when "0000" =>N<="10001000";<br /> when "0001" =>N<="11011011";<br /> when "0010" =>N<="10100010";<br /> when "0011" =>N<="10010010";<br /> when "0100" =>N<="11010001";<br /> when "0101" =>N<="10010100";<br /> when "0110" =>N<="10000100";<br /> when "0111" =>N<="11011010";<br /> when "1000" =>N<="10000000";<br /> when "1001" =>N<="10010000";<br /> when others =>N<="11111111";<br /> end case;<br />end process;<br /> <br />end Behavioral;<br />以上为源程序，当inc=‘0’时，应该加1的，但并没有加1，不知何原因？ |
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