LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SPDA IS PORT ( CLK,PHSEL0,PHSEL1 :IN STD_LOGIC; SDAA :OUT INTEGER RANGE 0 TO 127; PDAA :OUT INTEGER RANGE 0 TO 127); END;
ARCHITECTURE BEHV OF SPDA IS SIGNAL PHSEL :STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL SDAA_S :INTEGER RANGE 0 TO 127 :=0; SIGNAL PDAA_S :INTEGER RANGE 0 TO 127 :=0; BEGIN PHSEL <= PHSEL1 & PHSEL0; PROCESS(CLK,PHSEL) BEGIN IF ( CLK'EVENT AND CLK='1' ) THEN SDAA_S <= SDAA_S+1; CASE (PHSEL) IS WHEN "00" => PDAA_S <= SDAA_S+0; WHEN "01" => PDAA_S <= SDAA_S+32; WHEN "10" => PDAA_S <= SDAA_S+64; WHEN "11" => PDAA_S <= SDAA_S+96; END CASE; END IF; END PROCESS; SDAA <= SDAA_S-1; PDAA <= PDAA_S; END BEHV; |