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`timescale 1ns / 1ns<br /><br />/********************************************************************************<br />** 模块名称：24位计数器<br />** 功能描述：<br />********************************************************************************/<br />module counter(<br /> clk, //基准时钟<br /> fin, //转速信号输入<br /> dataout //发送的24bit数据 <br /> );<br /> input clk; //基准时钟<br /> input fin; //转速信号<br /> output [23:0]dataout;<br /> <br /> reg state;<br /> reg [23:0] dataoutbuf24; //转速信号缓存，转速信号输出<br /> reg [15:0] dataoutbuf16;<br /> reg [7:0] dataoutbuf8;<br /> reg latch_clr,setdata ; //<br /> wire cout16ove,ove;<br /> parameter zero = 16'd0,COUNT = 1'b0,LATCH_CLR = 1'b1 ; <br /> <br /><br /><br /><br /><br /> <br /> always @(posedge clk )<br /> begin<br /> case (state)<br /> COUNT: <br /> begin <br /> if(latch_clr)<br /> state <= LATCH_CLR;<br /> else<br /> begin<br /> if(!setdata) //无锁存溢出信号，正常+1<br /> begin<br /> dataoutbuf16 <= dataoutbuf16 + 1;<br /> if(cout16ove)<br /> dataoutbuf8 <= dataoutbuf8 + 1;<br /> end<br /> end<br /> state <= COUNT;<br /> end<br /> LATCH_CLR:<br /> begin<br /> dataoutbuf24 <= {dataoutbuf16,dataoutbuf8};<br /> dataoutbuf16 <= 16'd0;<br /> dataoutbuf8 <= 8'd0;<br /> latch_clr <= 0;<br /> setdata <= 0; //清 输出数据全1 使能位<br /> state <= COUNT;<br /> end<br /> default:state <= COUNT; <br /> endcase <br /> end<br /> <br /> assign dataout = dataoutbuf24;<br /> assign cout16ove = (&dataoutbuf16);<br /> assign ove = (&dataoutbuf16)&(&dataoutbuf8); <br /> <br /> <br /> <br /> always @(posedge fin)<br /> begin<br /> latch_clr <= 1'b1;<br /> end<br /> <br /> always @(posedge ove)<br /> begin<br /> setdata <= 1'b1;<br /> end<br /> <br />endmodule |
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