综合原理图，后两个always没有综合进去，高手指点

只看该作者 · 2009-7-2 09:05

`timescale 1ns / 1ns

/********************************************************************************
** 模块名称：24位计数器
** 功能描述：
********************************************************************************/
module counter(
   clk,         //基准时钟
   fin,         //转速信号输入
   dataout         //发送的24bit数据
   );
input   clk;       //基准时钟
input   fin;        //转速信号
output   [23:0]dataout;

reg    state;
reg    [23:0] dataoutbuf24;   //转速信号缓存，转速信号输出
reg    [15:0] dataoutbuf16;
reg    [7:0]  dataoutbuf8;
reg    latch_clr,setdata ;   //
wire   cout16ove,ove;
parameter       zero = 16'd0,COUNT = 1'b0,LATCH_CLR = 1'b1 ;



     always @(posedge clk  )
     begin
       case (state)
      COUNT:
          begin
           if(latch_clr)
              state <= LATCH_CLR;
             else
                 begin
                 if(!setdata)       //无锁存溢出信号，正常+1
                     begin
                  dataoutbuf16 <= dataoutbuf16 + 1;
                   if(cout16ove)
                   dataoutbuf8 <= dataoutbuf8 + 1;
                      end
               end
                 state <= COUNT;
            end
      LATCH_CLR:
           begin
            dataoutbuf24 <= {dataoutbuf16,dataoutbuf8};
          dataoutbuf16 <= 16'd0;
             dataoutbuf8 <= 8'd0;
           latch_clr <= 0;
             setdata <= 0;   //清  输出数据全1 使能位
             state <= COUNT;
             end
        default:state <= COUNT;
      endcase
     end

assign dataout = dataoutbuf24;
assign cout16ove = (&dataoutbuf16);
assign  ove = (&dataoutbuf16)&(&dataoutbuf8);

     always @(posedge fin)
    begin
     latch_clr <= 1'b1;
    end

     always @(posedge ove)
    begin
     setdata <= 1'b1;
     end

endmodule