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最早发在“英语角板块”的，那里人气不怎么样。放在这里，如果读完对你有帮助，请劳驾帮顶顶...<br /><br />限于本人水平有限，不妥之处请各位指正... :)<br /><br />译者：wolver<br />联系：wolver#21com.com (把#改为@)<br />转载请注明出处！<br /><br /><br />原文下载：<br /><a href="https://bbs.21ic.com/upfiles/img/20082/200822121123314.rar" target=_blank>https://bbs.21ic.com/upfiles/img/20082/200822121123314.rar</a><br /><br /><br />（翻译如下）<br /><br />High-Speed Backplanes Pose New Challenges to Comms Designers<br />【大多数设计师面临高速基板设计新挑战】<br /><br />专业名词汇总（此部分非原文内容）：<br />Backplanes：基板，不一定专指PCB，也可能包含集成电路(IC)的基板...（没找到合适的描述）<br />state-of-the-art ：暂翻译为“完美”（没搞懂）<br />reflections：反射<br />crosstalk：交叉干扰<br />skin effect：肌肤效应<br />dielectric loss：绝缘损耗<br />inter-symbol interference (ISI)：码间干扰<br />via stub effect：过孔效应<br />signal-integrity：信号完整性<br />PCB：印刷电路板<br />overdrive：过激励<br />ISI jitter：码间颤动(好像不太确切)<br />inter-pair skew：对间斜度(好像不太确切)<br />FR-4：一种PCB板材<br />ROGER：一种PCB板材<br />eye：眼图，测量信号完整性<br />adaptive filtering：自适应滤波器<br />Least Mean Square (LMS):最小均方值(LMS)<br /><br /><br />（以下是原文和翻译）<br />The operating data rates of current state-of-the-art backplane serial links are in the 2.5- to 3.125-Gbit/s range. As silicon becomes available that can support higher data rates into the 5- and 10-Gbit/s range, comm system designers are looking for ways to support these higher rates within their existing backplanes. <br />【当前完美的基板串行连接的数据率在2.5Gbit/s到3.125Gbit/s，而当硅导体使用时，达到5Gbit/s到10Gbit/s范围。大多数的系统设计师在现有基板条件下、不断寻找提升更高传输速率的办法...】<br /><br />In the 5- to 10-Gbit/s range, the technical challenges created by phenomenon such as reflections and crosstalk increase. In addition, new voltage- and timing-related challenges have arisen that typically do not exist in lower data rate ranges. These include skin effect, dielectric loss, inter-symbol interference (ISI), and via stub effect.<br />【在5Gbit/s到10Gbit/s范围，随着反射和交叉干扰现象的严重，现有技术面临挑战！另一方面，电压和时序关联被引入。当然，在低速率条件下可不考虑这些问题。它们包括：肌肤效应、绝缘损耗、码间干扰和过孔效应。】<br /><br />To overcome these challenges, system designers must develop accurate and efficient models for both the active and the passive components of the system. Silicon vendors also need channel models to successfully design proper on-chip circuits for implementing various techniques like equalization and reflection cancellation. By modeling the known deterministic effects of the channel, signal-integrity related problems can be understood, and techniques can be developed to minimize their impacts. <br />【为了解决这些难点，系统设计者们必须为有源和无源的系统中的元件开发出准确而有效的模块，半导体厂商也同样需要某些技术来设计出适合的信道模块、以解决均衡和反射问题，通过对已知有影响的信道建模分析，信号完整性的相关问题变得容易理解，并且这些已开发的技术手段可使问题最小化。】<br /><br />To develop a backplane model, individual models for connectors, packages, PCB traces and vias are needed. In this article, we'll examine the technical challenges that must be overcome to support 5- to 10-Gbit/s rates, and the corresponding channel model requirements. <br />【为了开发这种基板的技术模板，预先完善一些独立模板，诸如：连接器、封装、PCB连接线和过孔是有必要的。在本文中，我们将讨论解决支持5Gbit/s到10Gbit/s传输速率的难点、以及这些信道模板需要的必要条件。】<br /><br />Channel Impairments<br />【信道损失】<br /><br />As the data transfer rate on the channel increases, "old" problems are exacerbated, and "new" problems arise that must be addressed. Figure 1 shows the key timing and voltage related impairments that must be addressed as data rates increase. <br />【当信道数据传输率提高后，“老”问题恶化，“新”问题涌现，它们需要归类。图1归类了随着速率的增加导致的关键时序和和相关电压损失。】<br /><br />（译者注：下面这张图很经典！）<br /><br />Figure 1: Above 3 Gbit/s, backplane transmission becomes a major challenge.<br />【图1：超过3Gbit/s部分，基板传输变成主要难点。】<br /><br /><img src="http://img.cmpnet.com/commsdesign/csd/2004/jan04/rambus-fig1.jpg"><br /><br />Figure 1 is divided into three regions of interest: <br />【把图1分成三个有趣的区域】<br /><br />* The 100 Mbit/s to 1 Gbit/s region <br />【* 100Mbit/s到1Gbit/s区域】<br />* The 1 to 3 Gbit/s region <br />【* 1Gbit/s到3Gbit/s区域】<br />* The 3 to 10 Gbit/s region <br />【* 3Gbit/s到 10Gbit/s区域】<br /><br />The 100 -bit/s to 1-Git/s region is the better understood of the three. In this range the designer must compensate for the issues listed in the above drawing and remove fixed errors such as impedance mismatch and data/clock skew issues. <br />【100Mbit/s到1Gbit/s这个区域是三个区域中较容易理解的。在这个区域，设计者们必须补偿上图中诸如：阻抗匹配和数据、实钟前后边缘的斜度问题，以修正传输错误。】<br /><br />In the 1- to 3-Gbit/s range, the designer must make adjustments that are a function of the channel's electrical behavior, such as channel loss and distortion. These quantities are typically not known when the silicon is designed. Consequently, a feedback loop can be used to adjust the variables of concern. For example, the transmit driver output swing driving into a lossy channel can be adjusted by a feedback loop sensing the input swing at the far end receiver. The objective in this example is to overdrive the channel and compensate for its losses. <br />【在 1Gbit/s到3Gbit/s区域，设计者必须调整电路信道中的功能特性，如：信道损耗和失真。如此多的问题对半导体厂商都是未知的。然而，反馈环式的设计模式可以解决问题。例如：驱动器通过输出到有损耗信道中远点的接收器，再检测信号反馈给驱动器（这句是意翻，非直译）。例子中的方法就是采用过激励来补偿损耗。】<br /><br />Above 3 Gbit/s, the existing variables become harder to manage, and new variables begin to emerge as shown in the above drawing. These include skin effect, dielectric loss, intersymbol interference (ISI), via stub effect, ISI jitter, and inter-pair skew. Let's look at these six in more detail starting with skin effect.<br />【超过3Gbit/s速率，在上图中的已有的问题更难于掌控，而新问题也不端出现。它们包括：肌肤效应、绝缘损耗、码间干扰(ISI)、过孔效应、码间干扰颤动和对间斜度。让我们从肌肤效应这六个要素之一开始分析它们。】<br /><br />1. Skin Effect<br />【1、肌肤效应】<br /><br />Skin effect is a physical phenomenon related to high frequency transmission on a wire. At very high frequencies, the electromagnetic field of the wire causes most of the electrical current to become crowded at the edges of the wire. This phenomenon alters the distribution of the signal current throughout the wire and changes the effective resistance on the wire. The resulting effect is increased signal attenuation at higher frequencies. <br />【肌肤效应是在一条线路中高频率传输表现的物理现象。在非常高的频率下，导线的电磁场使电场电流汇聚在导线边界。这一现象改变了通过导线的电流分布、从而改变导线的阻抗，结果是使信号在高频下衰减。】<br /><br />2. Dielectric Loss <br />【2、绝缘损耗】<br /><br />There are a number of PCB dielectric materials on the market today. The amount of dielectric loss in the material greatly affects signal integrity at high speeds. The lower the amount of dielectric loss, the less negative impact on the signal. <br />【现在市场上的大多数PCB绝缘材料，它们的总绝缘损耗在高速情况都严重影响信号完整性。绝缘损耗越低、对信号的负面影响越小。】<br /><br />Figure 2 shows the total loss (conductor + dielectric) on a given trace at different speeds. The signal amplitude transfer function (output divided by input signal) is normalized at 1 where there is no attenuation in the channel. <br />【图2展示了一段导线在不同速度下的总损耗（导体和绝缘体）。令信道中没有衰减的信号幅度为1，可以看出传输特性（输出由输入来区分）】<br /><br /><br />Figure 2: Loss as a function of frequency. <br />【图2：频率参照下的损耗特性】<br /><br /><img src="http://img.cmpnet.com/commsdesign/csd/2004/jan04/rambus-fig2.jpg"><br /><br />Between 1 and 100 MHz, the amount of conductor and dielectric loss is negligible. Throughout this range, the signal transfer function remains at about 1. At 1 GHz the signal has decreased to approximately 0.5, half of its original strength. At speeds above 5 GHz the signal strength drops below 0.2, losing approximately 80% of its original strength. Thus, losses are a major issue at these high frequencies. <br />【在1MHz到100MHz之间，导体和绝缘损耗的总量是可忽略的。在这个范围内，信号的传输特征维持在1。到1GHz时，信号衰减约到0.5，即一半的正常信号强度。。速度超过5GHz，信号强度跌到0.2以下，即损失约80%的正常信号强度。因此，损耗在这样的高频应用下，才是主要问题。】<br /><br />Although FR4 is the most commonly used material, it clearly does not have the best electrical characteristics when measured in terms of dielectric loss, as shown in the Figure 3. Still, FR4 is generally preferred due to its lower production costs. <br />【尽管FR4是大多数常用的材料，明显的在绝缘损耗方面没有较好的特性，从图3可以看出来。然而，FR4仍然是低成本产品的首选。】<br /><br />Figure 3: trace loss with FR-4 and Roger dielectrics.<br />【图3：FR-4与罗杰的绝缘损耗轨迹表】<br /><br /><img src="http://img.cmpnet.com/commsdesign/csd/2004/jan04/rambus-fig3.jpg"><br /><br />3. Intersymbol Interference<br />【3、码间干扰(ISI)】<br /><br />ISI is a phenomenon caused by the different propagation velocities of low and high frequencies throughout a channel. The end result is a spreading of bits, also known as pulse spreading. Stated differently, transmitting a square pulse through such a channel results in a widening and flattening of the pulse at the far end. This implies that each data bit of information overlaps with its adjacent bits. This overlap can cause major distortions of the signal. At high data rates and in long channels, the ISI can be so bad that it becomes impossible to recognize an eye pattern on the oscilloscope. This is a major phenomenon limiting data transmission, and must generally be addressed starting at the 2 to 3 Gbit data rates in most system backplanes. <br />【ISI是不同传播速率下的高低频信号通过一个通道形成的物理现象。表现在传输多个比特位，通常以脉冲形式传播。与静态不同，发送一个方波脉冲给一个通道，结果是在终端被展宽并压扁。这意味着数据的位信息被他们临近的位干涉。这种干涉是主要的信号失真。在高数据率和长信道下，ISI非常糟，以至示波镜眼图无法识别。这一现象限制了数据的传输，在大多数基板系统里，他们通常表现在2GHz到3GHz这个范围。】<br /><br />4. Via Stub Effect <br />【4、过孔效应】<br /><br />At high frequencies, via stubs can cause reflections in the signal. These stubs are common on all PCBs, but at lower speeds their effects are negligible. The thicker the backplane traces, the larger the via stubs, which in turn causes the amount of signal reflections to increase. Ideally, the stub length, and resulting stub delay, should be kept as short as possible. <br />【在高频段，过孔同样影响信号。这些暗桩在大多数的PCB里，对于低速信号的影响可忽略。较密集的线、较大的过孔，他们翻转后导致信号反射总量增加。理论上讲，暗桩的长度和延时关联，应让它们尽量的短。】<br /><br />5. ISI Jitter<br />【5、ISI 颤动】<br /><br />ISI jitter is caused by intersymbol interference. Because the pulse's energy is seen to spread into the adjacent bits with ISI, this energy will combine with the previous and next bits respectively. The adding or subtracting of energy depends on the logical value of the current pulse, and the logical values of the previous and next bits. Since the amount of energy in each bit period varies as a result, the transition time between bits also varies. A movement in time of this transition time is called jitter. Therefore, bit-dependent jitter can result. This is known as ISI jitter. <br />【ISI颤动时ISI的产物。因为脉冲能量通过ISI传播给了它临近的位，这种能量与先前位和下一位逐个结合。能量的增加和减少取决于当前脉冲的逻辑值、先前和下一个脉冲的逻辑值。由于每一个位的能量周期的变化，位间时间也同样变化。这种传送时间的移动就叫颤动。因此，位颤动就发生了。这就是“家喻户晓”的ISI颤动。】<br /><br />6. Intra-pair skew<br />【6、内联对斜率】<br /><br />Intra-pair skew is the amount of skew between the two signals of a differential pair. This skew can be caused by variables such as a length mismatch between traces, non-uniform bends in the signal traces, via stubs, and via transitions. <br />Skew is normally measured as a percentage of the Unit Interval (UI). Even a slight amount of skew can dramatically impact the percentage of UI at high frequencies. For example, a 1% skew for a 30-inch trace correlates to a 5% UI mismatch at 1 Gbit/s and a 50% UI mismatch at 10 Gbit/s. This, in turn, reduces the data eye opening and increases the amount of jitter. <br />【内联对斜率是一组差分对的两个信号的总斜率。它可能由于长度匹配不同、不一致的弯曲、过孔数、过孔跳跃而影响。<br />斜率通常用内部单位(UI)百分比来测量。有时轻微的斜率变化都会对高频的UI百分率产生戏据性的影响。举例：对30英寸的线来说，1%的斜率变化关系到1Gbit/s的5% UI失配，关系到10Gbit/s的50% UI失配。这点，从另一个角度来说，缩减了眼图的扩展度，并增加总量颤动。】<br /><br /><br />（译者注：看懂以下部分需要懂得反馈控制和数字滤波器等一些基本常识）<br /><br />Equalization: Mitigating Impairments<br />【均衡：缩减损耗】<br /><br />Many of the channel impairments described above can be mitigated on-chip using equalization. This term is used to define circuits that can attenuate low frequencies and amplify high frequencies in either the transmit or receive directions, or both. <br />【以上描述的许多通道损耗可通过均衡法得到片内减轻。这个术语用来定义那些低频率和振幅、高频率的单向或双向传输】<br /><br />In one form of receive equalization, the incoming signal is sampled at different delay points. At each delay point, the signal is multiplied by a predetermined coefficient value. Each of the resulting values are then summed together to effectively recreate the signal as if it had just left the transmitter, effectively negating the effects of the various channel impairments described above. <br />【对于接收均衡，要输入的信号在不同的延时点采样。在每个延时点，采样值乘一个预定的系数。再将结果加在一起重建信号，然后从发送端输出，这样可以有效的弥补上面描述的那些不同的通道损耗。】<br /><br />Receive equalization is typically performed using a digital or analog adaptive filtering method. The equalization circuit examines the filtered signal output and adjusts the coefficients to optimize the signal quality through a feedback loop. <br />【接收均衡典型的招式是用数字或模拟自适应滤波器。均衡电路测试滤波信号的输出来调整系数以便优化通过信号反馈环路的质量。】<br /><br />In contrast to the receive equalizer, the transmit equalizer boosts the high frequencies of a signal by a fixed amount before it is sent out. In theory, the negative effects of the previously mentioned variables will occur on the boosted portion of the signal, thereby allowing the overall signal quality at the receiver to more closely resemble that which was sent out by the transmitter. In other words, the transmitter pre-distorts the signal in the opposite way from that created in the channel so that a better quality signal can be seen at the receiver. <br />【与接收均衡不同，发送均衡在信号送出前，提升一个固定总量的高频。理论上，只会给前面提到的那部分提升的信号带来负面影响，从而允许接收端收到的信号品质与传送端发出的十分接近类似。换句话说，传送端预加重一个与传输通道反特性的信号，通过抵消、接收端可以获得较好的信号质量。】<br /><br />In both the transmit and receive path, there are two ways to set equalizer coefficients. The first is manual equalization. Also known as "set and forget", this coefficient setting technique is based on manual channel measurements. It can also be calculated on the basis of a single-bit-response (SBR) test through the channel. <br />【在收发双向路径时，有两种方式设置均衡系数。第一是手动均衡。也就是众所周知的“猴子搬包谷”，基于手动通道测量，这个系数的设置需要点技巧。它也可以基于信号位(SBR)通道响应来计算。】<br /><br />The second method is to use an adaptive equalization approach. By using an adaptive algorithm such as Least Mean Square (LMS), the equalizer can optimize the signal quality by modifying the coefficients on a continuous basis. This allows the equalizer to adapt to changing conditions in the back-plane. A continuously adaptive method is far superior than the "set and forget" method because it adjusts to the changing environment automatically. This is relevant because environmental effects such as temperature and humidity changes can have a dramatic impact on the channel behavior. <br />【第二种办法是用自适应均衡逼近。通过使用自适应算法，如：最小均方值(LMS)，通过连续信号的点的系数不断修正，均衡器就能优化信号质量。这样均衡器就适应了基板系统不断变化的情况。这种不断适应的方法明显优越“猴子搬包谷”，那是因为它自动调整应用环境的变化。这些变化都是关联的，因为环境的因素，比如：温度、湿度都能对通道的特性产生戏剧性的影响。】<br /><br />System Modeling<br />【系统模型】<br /><br />Each of the points discussed above indicates an electrical variable that can impact signal integrity over the backplane. To effectively manage the negative effects at each of these points, the physical structures impacting these electrical variables should be modeled. Once each physical structure is modeled (package, trace, via, etc.) an overall system model can be developed that is representative of the point-to-point trace from device to device.<br />【以上讨论的要点显示了解决基板系统信号完整信的要素。要有效的掌控每个要点的负面影响，需要建模来解决这些电路中的可变因素。一旦建立模型（封装、导线、过孔等），那么具有代表性的全方位系统模型就可以用来开发了。】<br /><br />Figure 4 shows a flow chart of the modeling process. <br />【图4展示了建模处理的过程图表】<br /><br /><img src="http://img.cmpnet.com/commsdesign/csd/2004/jan04/rambus-fig4.jpg"><br /><br /><br />The flow chart shown in Figure 4 includes test structures, 2D/3D simulations, a channel model, a system model, test chips, and system simulations. Let's look at each block in more detail. <br />【图4的图表包含了测试结构、2D/3D仿真、通道模、系统模、测试芯片和系统仿真。让我们来看看每个模块的更多细节。】<br />1. Test Structures<br />【1、测试结构】<br /><br />The test structures include measurements that have been made at the various points in the signal path. These include package-to-board via, line card trace, line card via, backplane connector, backplane via, and backplane trace. <br />【测试结构包含信号路径上不同的点的测量方法。它们是：封装到基板过孔、线卡导线、线卡过孔、基板连接器、基板过孔和基板导线。】<br /><br />Physical measurements are made on the electrical characteristics of each variable. Data from these measurements are then used to construct the overall channel model. <br />【物理测量方法由每个不同的电特征而定制。测量的数据用来构建全面的通道模型。】<br /><br />2. 2D and 3D Simulations<br />【2、2D和3D仿真】<br /><br />Another way to develop component models is via 2- or 3-dimensional simulation. In this case the simulator takes the size, length, thickness, and other relevant physical parameters and calculates the relative electrical characteristics for that component. These two types of models are then used to build the channel model shown in Figure 4. <br />【另外一种开发元件模型的方法是通过2维和3维的仿真。在这种情形下，仿真尺寸、长度、厚度和其它关联参数，并计算关联的元件电特征。这就是图4显示的两种构建通道模的方法。】<br /><br />3. Channel Model<br />【3、通道模型】<br /><br />The channel model includes everything except the silicon devices on each end. The channel model is built and tested and the results are compared against a measured channel response to determine whether the model is working correctly. Based on this correlation, the channel model is modified to match the results of the physical measurements. The goal is to have an accurate channel model at the frequencies of interest such that it can be used reliably as a predictor of behavior when simulating the entire system. <br />【通道模型含盖了除硅半导体设备外的所以东西。通道模型构建和测试的结果用来对比实测的通道响应，以决定模型是否工作正常。基于这种关系，通道模型需要不断修改以匹配实际的测量。当仿真完整系统时，精确的通道模型需要时刻关注那些可预料的变化因素，以确保可靠。】<br /><br />4. System model and Active Signal Integrity Techniques<br />【4、系统模型和主动式信号完整性技术】<br /><br />The system model includes not only the channel model, but also the silicon devices at each end. At data rates below 1 Gbit/s, the system model and the channel model should indicate in most cases that the signal degradation can be addressed using standard fixed or feedback techniques, as discussed earlier. Above 1 Gbit/s, additional signal integrity (SI) techniques must be employed to maintain overall signal quality. <br />【系统模型包含的不仅是通道模型，同样包含最终应用的半导体设备模型。在1Gbit/s数据率以下，系统和通道的模型表明：大多数的信号退化情形可以通过标准的固定或反馈技术来展示它们，像先前讨论过的1Gbit/s情况，附加的信号完整性(SI)技术必须用来解决整个系统的信号质量问题。】<br /><br /><br />Active SI, or equalization, is required if the channel model simulation output dictates that additional steps must be taken to eliminate signal degradation. This is often the case above 1 Gbit/s, and generally always required in most systems above 3 Gbit/s. <br />【主动式SI，或均衡技术是需要的，一旦通道模型仿真需要附加解决信号退化的问题。这在1Gbit/s以上是司空见惯的事，而在大多数3Gbit/s系统是家常便饭。】<br /><br />4. Test chips and System Measurements<br />【4、测试芯片和系统测量法】<br /><br />Once the active SI algorithm and circuit has been developed, test chips can be built to demonstrate that the equalization algorithms are working properly. System measurements can be taken on the test chip and on the overall system to ensure signal integrity from chip-to-chip. These results are then correlated to the system model to ensure the accuracy of the models. <br />【一旦主动式SI算法和电路开发出来，那么就可以开发测试芯片来验证等效的算法是否工作正常。系统测量方法就在测试片内生效，以便确定整个系统“片到片”的信号完整性。这些测试结果有助于提高系统模型的精确性。】<br /><br />5. System Simulations<br />【5、系统仿真】<br /><br />With a well-correlated and stable system model, the overall system simulation can be done. The system simulation takes into account other variables such as: <br />【由于有合理和稳定的系统模型，系统全面仿真得以实施。系统仿真可以专注于另外的变化因素，如：<br /><br />Size of the channels in the chassis Number of potential cards <br />【通道框架的尺寸能容纳的潜在的卡（不明白嘛意思）】<br /><br />Shortest distance over the backplane from card-to-card <br />【基板“卡到卡”的最短距离】<br /><br />Longest distance over the backplane from card-to-card <br />【基板“卡到卡”的最长距离】<br /><br /><br />Using this information, the system simulator can interpolate the electrical characteristics for all other points in the chassis. For example, if the electrical characteristics between two points are measured, with the shortest distance being two inches and the longest distance being 10 inches, the system simulator can be used to calculate the electrical characteristics for all other points in between, provided a good system model has been built. <br />【使用这些信息，系统仿真可以给框架内的其它点添加电特征。举例：如果两点间的电特征已经测量到、最短2英寸最长10英寸，系统仿真器就可以计算其它点的电特征。当然，前提是我们有个好的系统模型。】<br /><br />Wrap Up<br />【总结一下】<br /><br />The backplane is a complex system containing a number of variables that can impact signal integrity. The overall number of variables to be managed and the negative impact they have on signal quality increases with speed. At speeds over 3 Gbps, not only are the negative impact of existing variables increased, but new variables such as skin effect, dielectric loss, ISI, and via stub effect, must be taken into account.<br />【基板系统是个包含有许多削减信号完整信的复杂系统，随着速度的提高，许多负面的削减信号完整性的变数需要掌控。在3Gbit/s以上，不仅现有的负面因素增加，绝缘损耗、ISI和过孔效应，也必须计算在内。】<br /><br />The addition of physical components within a given point-to-point link also causes signal degradation. These include PCB traces, connectors, via stubs, and the actual silicon devices themselves. Each time another impairment is factored in, signal quality is reduced at high frequencies. <br />【附加的在已知的点对点连接同样导致信号退化。它们包含：PCB导线、连接器、过孔、真实的半导体设备。每次这些因素参合进来，高频信号完整性递减。】<br /><br />To overcome these challenges, system vendors must develop accurate and well-correlated models for both the active and the passive components of the system. Silicon vendors need quality channel models to successfully design proper on-chip circuits for implementing various techniques like equalization and reflection cancellation. By modeling all the known deterministic effects of the channel, signal-integrity related problems can be well understood and minimized. <br />【为克服这些问题，系统卖家们必须开发出精确并合理的相关模型来适应有源和无源的元件系统。半导体商需要高品质的通道模型以便成功设计正确的单片电路、来实现像均衡和反射消除的技术。通过对确定通道和信号完整性建模，相关问题将易于理解并最小化。】<br /><br />About the Author<br />【作者简介】<br /><br />Jean-Marc Patenaude is a technical marketing director in Rambus' Logic Interface Division. He holds a Bachelor of Science degree in electrical engineering from the University of Waterloo and a Master of Science degree in electronics from Carleton University. Jean-Marc can be reached at jmp@rambus.com<br />【Jean-Marc Patenaude现任Rambus公司逻辑接口区域技术市场总监。曾获沃特卢(美国衣阿华州东北部城市)大学电子工程理工学士学位和Carleton大学电子学理工硕士学位。用jmp@rambus.com可以联系到他。】<br /><br />(始于2008-02-23，全文完 :) |
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