在ModelSim中如何仿真带有IP核的程序呢？

只看该作者 · 2008-5-9 21:19

程序中调用了Flash Memeory模块，方针的时候出现了错误，不知道怎么回事？
错误信息如下：
# Loading presynth.test_lut_dds
# Loading presynth.lut_dds
# Loading presynth.sin_rom
# ** Error: (vsim-3033) E:/DDC_NCO/lut_dds/sourse/lut_dds/smartgen/sin_rom/sin_rom.v(89): Instantiation of 'NVM' failed. The design unit was not found.
#         Region: /test_lut_dds/my_lut_dds/sin_wave
#         Searched libraries:
#             E:\DDC_NCO\lut_dds\sourse\lut_dds\simulation\presynth
# ** Error: (vsim-3033) E:/DDC_NCO/lut_dds/sourse/lut_dds/smartgen/sin_rom/sin_rom.v(90): Instantiation of 'GND' failed. The design unit was not found.
#         Region: /test_lut_dds/my_lut_dds/sin_wave
#         Searched libraries:
#             E:\DDC_NCO\lut_dds\sourse\lut_dds\simulation\presynth
# ** Error: (vsim-3033) E:/DDC_NCO/lut_dds/sourse/lut_dds/smartgen/sin_rom/sin_rom.v(91): Instantiation of 'VCC' failed. The design unit was not found.
#         Region: /test_lut_dds/my_lut_dds/sin_wave
#         Searched libraries:
#             E:\DDC_NCO\lut_dds\sourse\lut_dds\simulation\presynth
# Loading presynth.cos_rom
# ** Error: (vsim-3033) E:/DDC_NCO/lut_dds/sourse/lut_dds/smartgen/cos_rom/cos_rom.v(89): Instantiation of 'NVM' failed. The design unit was not found.
#         Region: /test_lut_dds/my_lut_dds/cos_wave
#         Searched libraries:
#             E:\DDC_NCO\lut_dds\sourse\lut_dds\simulation\presynth
# ** Error: (vsim-3033) E:/DDC_NCO/lut_dds/sourse/lut_dds/smartgen/cos_rom/cos_rom.v(90): Instantiation of 'GND' failed. The design unit was not found.
#         Region: /test_lut_dds/my_lut_dds/cos_wave
#         Searched libraries:
#             E:\DDC_NCO\lut_dds\sourse\lut_dds\simulation\presynth
# ** Error: (vsim-3033) E:/DDC_NCO/lut_dds/sourse/lut_dds/smartgen/cos_rom/cos_rom.v(91): Instantiation of 'VCC' failed. The design unit was not found.
#         Region: /test_lut_dds/my_lut_dds/cos_wave
#         Searched libraries:
#             E:\DDC_NCO\lut_dds\sourse\lut_dds\simulation\presynth
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./run.do PAUSED at line 17

只看该作者 · 2008-5-10 19:21

请检查程序中是否定义了GND VCC 和NVM,Libero集成的modelsim已经包含了ACTEL的仿真库，可以直接仿真

只看该作者 · 2008-5-21 23:32

   参考书上《Flash Memry实验》，主程序模块中没有定义VCC,GND之类的信号，是不是在测试激励文件中要定义？

我的测试文件：
// test_Lut_DDFS.v
`timescale 1ns / 1ns

module test_Lut_DDFS;

reg clk;
reg reset;
reg [19:0] freq_words;
reg [9:0] phase_words;

wire [15:0] ddfs_sin_out;     //正弦信号输出
wire [15:0] ddfs_cos_out;      //余弦信号输出

//实例化
Lut_DDFS my_Lut_DDFS(
                    .clk(clk),
                    .reset(reset),
                    .freq_words(freq_words),
                    .phase_words(phase_words),
                    .ddfs_sin_out(ddfs_sin_out),
                    .ddfs_cos_out(ddfs_cos_out)
                   );

//周期性时钟
initial clk = 0;
always #5 clk = ~clk;

//测试数据
initial
begin
    //初始化
    reset = 1;
    freq_words = 0;
    phase_words = 0;
    //测试数据变化
  #12
    freq_words = 20'b00000100100000000000;
    phase_words = 10'b1000000000;
  #6
    reset = 0;
end
endmodule

  还有，我用ModelSim仿真《Flash Memory实验》时，发现那个测试激励文件很繁琐，其中包括tb_clock_minmax，stimulus这些模块，不是很明白。

在ModelSim中如何仿真带有IP核的程序呢？

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