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/*<br /> * vivi/arch/s3c2440/head.S:<br /> * Initialise hardware<br /> *<br /> * Copyright (C) 2001 MIZI Research, Inc.<br /> *<br /> * This program is free software; you can redistribute it and/or modify<br /> * it under the terms of the GNU General Public License as published by<br /> * the Free Software Foundation; either version 2 of the License, or<br /> * (at your option) any later version.<br /> *<br /> * This program is distributed in the hope that it will be useful, <br /> * but WITHOUT ANY WARRANTY; without even the implied warranty of<br /> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the <br /> * GNU General Public License for more details.<br /> *<br /> * You should have received a copy of the GNU General Public License <br /> * along with this program; if not, write to the Free Software<br /> * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA<br /> *<br /> *<br /> * Author: Janghoon Lyu <nandy@mizi.com><br /> * Date : $Date: 2004/02/04 06:22:24 $<br /> *<br /> * $Revision: 1.1.1.1 $<br /> *<br /> *<br /> * History:<br /> *<br /> * 2002-05-14: Janghoon Lyu <nandy@mizi.com><br /> * - Initial code<br /> *<br /> */<br /><br />#include "config.h"<br />#include "linkage.h"<br />#include "machine.h"<br /><br />@ Start of executable code <br /><br />ENTRY(_start)<br />ENTRY(ResetEntryPoint)<br /><br />@<br />@ Exception vector table (physical address = 0x00000000)<br />@<br /><br />@ 0x00: Reset<br /> b Reset<br /><br />@ 0x04: Undefined instruction exception<br />UndefEntryPoint:<br /> b HandleUndef<br /><br />@ 0x08: Software interrupt exception<br />SWIEntryPoint:<br /> b HandleSWI<br /><br />@ 0x0c: Prefetch Abort (Instruction Fetch Memory Abort)<br />PrefetchAbortEnteryPoint:<br /> b HandlePrefetchAbort<br /><br />@ 0x10: Data Access Memory Abort<br />DataAbortEntryPoint:<br /> b HandleDataAbort<br /><br />@ 0x14: Not used<br />NotUsedEntryPoint:<br /> b HandleNotUsed<br /><br />@ 0x18: IRQ(Interrupt Request) exception<br />IRQEntryPoint:<br /> b HandleIRQ<br /><br />@ 0x1c: FIQ(Fast Interrupt Request) exception<br />FIQEntryPoint:<br /> b HandleFIQ<br /><br />@<br />@ VIVI magics<br />@<br /><br />@ 0x20: magic number so we can verify that we only put <br /> .long 0<br />@ 0x24:<br /> .long 0<br />@ 0x28: where this vivi was linked, so we can put it in memory in the right place<br /> .long _start<br />@ 0x2C: this contains the platform, cpu and machine id<br /> .long ARCHITECTURE_MAGIC<br />@ 0x30: vivi capabilities <br /> .long 0<br />#ifdef CONFIG_PM<br />@ 0x34:<br /> b SleepRamProc<br />#endif<br />#ifdef CONFIG_TEST<br />@ 0x38:<br />@ b hmi<br />#endif<br /><br /><br />@<br />@ Start VIVI head<br />@<br />Reset:<br /> @ disable watch dog timer<br /> mov r1, #0x53000000<br /> mov r2, #0x0<br /> str r2, [r1]<br /><br /> @ disable all interrupts<br /> mov r1, #INT_CTL_BASE<br /> mov r2, #0xffffffff<br /> str r2, [r1, #oINTMSK]<br /> ldr r2, =0x7ff<br /> str r2, [r1, #oINTSUBMSK] <br /><br /> @ initialise system clocks<br /> mov r1, #CLK_CTL_BASE<br /> mvn r2, #0xff000000<br /> str r2, [r1, #oLOCKTIME]<br /> <br /> mov r1, #CLK_CTL_BASE<br /> ldr r2, clkdivn_value<br /> str r2, [r1, #oCLKDIVN]<br /><br /> mrc p15, 0, r1, c1, c0, 0 @ read ctrl register <br /> orr r1, r1, #0xc0000000 @ Asynchronous <br /> mcr p15, 0, r1, c1, c0, 0 @ write ctrl register<br /><br /> mov r1, #CLK_CTL_BASE<br /> @ldr r2, mpll_value @ clock default<br /> ldr r2, =0x7f021 @mpll_value_USER @ clock user set<br /> str r2, [r1, #oMPLLCON]<br /> bl memsetup<br /><br /><br />#ifdef CONFIG_PM<br /> @ Check if this is a wake-up from sleep<br /> ldr r1, PMST_ADDR<br /> ldr r0, [r1]<br /> tst r0, #(PMST_SMR)<br /> bne WakeupStart<br />#endif<br /><br /> @ All LED on<br /> mov r1, #GPIO_CTL_BASE<br /> add r1, r1, #oGPIO_F<br /> ldr r2,=0x55aa<br /> str r2, [r1, #oGPIO_CON]<br /> mov r2, #0xff<br /> str r2, [r1, #oGPIO_UP]<br /> mov r2, #0x00<br /> str r2, [r1, #oGPIO_DAT]<br /><br />#if 0<br /> @ SVC<br /> mrs r0, cpsr<br /> bic r0, r0, #0xdf<br /> orr r1, r0, #0xd3<br /> msr cpsr_all, r1<br />#endif<br /><br /> @ set GPIO for UART<br />#ifdef CONFIG_S3C2440_SMDK<br /> mov r1, #GPIO_CTL_BASE<br /> add r1, r1, #oGPIO_H<br /> ldr r2, gpio_con_uart <br /> str r2, [r1, #oGPIO_CON]<br /> ldr r2, gpio_up_uart<br /> str r2, [r1, #oGPIO_UP] <br />#endif<br /> bl InitUART<br /><br />#ifdef CONFIG_DEBUG_LL<br /> @ Print current Program Counter<br /> ldr r1, SerBase<br /> mov r0, #'\r'<br /> bl PrintChar<br /> mov r0, #'\n'<br /> bl PrintChar<br /> mov r0, #'@'<br /> bl PrintChar<br /> mov r0, pc<br /> bl PrintHexWord<br />#endif<br /><br />#ifdef CONFIG_S3C2440_NAND_BOOT<br /> bl copy_myself<br /><br />#if 1<br /> mov r1, #GPIO_CTL_BASE<br /> add r1, r1, #oGPIO_F<br /> mov r2, #0x00<br /> str r2, [r1, #oGPIO_DAT]<br />#endif<br /><br /> @ jump to ram<br /> ldr r1, =on_the_ram<br /> add pc, r1, #0<br /> nop<br /> nop<br />1: b 1b @ infinite loop<br /><br />on_the_ram:<br />#endif<br /><br />#ifdef CONFIG_DEBUG_LL<br /> ldr r1, SerBase<br /> ldr r0, STR_STACK<br /> bl PrintWord<br /> ldr r0, DW_STACK_START<br /> bl PrintHexWord<br />#endif<br /><br /> @ get read to call C functions<br /> ldr sp, DW_STACK_START @ setup stack pointer<br /> mov fp, #0 @ no previous frame, so fp=0<br /> mov a2, #0 @ set argv to NULL <br /><br /> bl main @ call main <br /><br /> mov pc, #FLASH_BASE @ otherwise, reboot<br /><br />@<br />@ End VIVI head<br />@<br /><br />/*<br /> * subroutines<br /> */<br /><br />@<br />@ Wake-up codes<br />@<br />#ifdef CONFIG_PM<br />WakeupStart:<br /> @ Clear sleep reset bit<br /> ldr r0, PMST_ADDR<br /> mov r1, #PMST_SMR<br /> str r1, [r0]<br /><br /> @ Release the SDRAM signal protections<br /> ldr r0, PMCTL1_ADDR<br /> ldr r1, [r0]<br /> bic r1, r1, #(SCLKE | SCLK1 | SCLK0)<br /> str r1, [r0]<br /><br /> @ Go...<br /> ldr r0, PMSR0_ADDR @ read a return address<br /> ldr r1, [r0]<br /> mov pc, r1<br /> nop<br /> nop<br />1: b 1b @ infinite loop<br /><br />SleepRamProc:<br /> @ SDRAM is in the self-refresh mode */<br /> ldr r0, REFR_ADDR<br /> ldr r1, [r0]<br /> orr r1, r1, #SELF_REFRESH<br /> str r1, [r0]<br /><br /> @ wait until SDRAM into self-refresh<br /> mov r1, #16<br />1: subs r1, r1, #1 <br /> bne 1b<br /><br /> @ Set the SDRAM singal protections<br /> ldr r0, PMCTL1_ADDR<br /> ldr r1, [r0]<br /> orr r1, r1, #(SCLKE | SCLK1 | SCLK0)<br /> str r1, [r0]<br /><br /> /* Sleep... Now */<br /> ldr r0, PMCTL0_ADDR<br /> ldr r1, [r0]<br /> orr r1, r1, #SLEEP_ON<br /> str r1, [r0] <br />1: b 1b<br /><br />#ifdef CONFIG_TEST<br />hmi:<br /> ldr r0, PMCTL0_ADDR<br /> ldr r1, =0x7fff0<br /> str r1, [r0]<br /> <br /> @ All LED on<br /> mov r1, #GPIO_CTL_BASE<br /> add r1, r1, #oGPIO_F<br /> ldr r2,=0x55aa<br /> str r2, [r1, #oGPIO_CON]<br /> mov r2, #0xff<br /> str r2, [r1, #oGPIO_UP]<br /> mov r2, #0xe0<br /> str r2, [r1, #oGPIO_DAT]<br />1: b 1b<br />#endif<br /><br />#endif<br /><br />ENTRY(memsetup)<br /> @ initialise the static memory <br /><br /> @ set memory control registers<br /> mov r1, #MEM_CTL_BASE<br /> adrl r2, mem_cfg_val<br /> add r3, r1, #52<br />1: ldr r4, [r2], #4<br /> str r4, [r1], #4<br /> cmp r1, r3<br /> bne 1b<br /> mov pc, lr<br /><br /><br />#ifdef CONFIG_S3C2440_NAND_BOOT<br />@<br />@ copy_myself: copy vivi to ram<br />@<br />copy_myself:<br /> mov r10, lr<br /><br /> @ reset NAND<br /> mov r1, #NAND_CTL_BASE<br /> ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )<br /> str r2, [r1, #oNFCONF]<br /> ldr r2, [r1, #oNFCONF]<br /><br /> ldr r2, =( (1<<4)|(0<<1)|(1<<0) ) @ Active low CE Control <br /> str r2, [r1, #oNFCONT]<br /> ldr r2, [r1, #oNFCONT]<br /><br /> ldr r2, =(0x6) @ RnB Clear<br /> str r2, [r1, #oNFSTAT]<br /> ldr r2, [r1, #oNFSTAT]<br /> <br /> mov r2, #0xff @ RESET command<br /> strb r2, [r1, #oNFCMD]<br /> mov r3, #0 @ wait <br />1: add r3, r3, #0x1<br /> cmp r3, #0xa<br /> blt 1b<br />2: ldr r2, [r1, #oNFSTAT] @ wait ready<br /> tst r2, #0x4<br /> beq 2b<br /><br /> ldr r2, [r1, #oNFCONT]<br /> orr r2, r2, #0x2 @ Flash Memory Chip Disable<br /> str r2, [r1, #oNFCONT]<br /><br /> @ get read to call C functions (for nand_read())<br /> ldr sp, DW_STACK_START @ setup stack pointer<br /> mov fp, #0 @ no previous frame, so fp=0<br /><br /> mov r1, #GPIO_CTL_BASE<br /> add r1, r1, #oGPIO_F<br /> mov r2, #0xe0<br /> str r2, [r1, #oGPIO_DAT]<br /><br /><br /> @ copy vivi to RAM<br /> ldr r0, =VIVI_RAM_BASE<br /> mov r1, #0x0<br /> mov r2, #0x20000<br /> bl nand_read_ll<br /><br />#if 1<br /> mov r1, #GPIO_CTL_BASE<br /> add r1, r1, #oGPIO_F<br /> mov r2, #0xb0<br /> str r2, [r1, #oGPIO_DAT]<br />#endif<br /><br /><br /> tst r0, #0x0<br /> beq ok_nand_read<br />#ifdef CONFIG_DEBUG_LL<br />bad_nand_read: <br /> ldr r0, STR_FAIL<br /> ldr r1, SerBase<br /> bl PrintWord<br />1: b 1b @ infinite loop <br />#endif<br /> <br />ok_nand_read:<br />#ifdef CONFIG_DEBUG_LL<br /> ldr r0, STR_OK<br /> ldr r1, SerBase<br /> bl PrintWord<br />#endif<br /><br /> @ verify<br /> <br /> mov r0, #0<br /> ldr r1, =0x33f00000<br /> mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes<br />go_next:<br /> ldr r3, [r0], #4<br /> ldr r4, [r1], #4<br /> teq r3, r4<br /> bne notmatch<br /> subs r2, r2, #4<br /> beq done_nand_read <br /> bne go_next<br />notmatch:<br />#ifdef CONFIG_DEBUG_LL<br /> sub r0, r0, #4<br /> ldr r1, SerBase<br /> bl PrintHexWord<br /> ldr r0, STR_FAIL<br /> ldr r1, SerBase<br /> bl PrintWord<br />#endif<br />1: b 1b<br />done_nand_read:<br /><br />#ifdef CONFIG_DEBUG_LL<br /> ldr r0, STR_OK<br /> ldr r1, SerBase<br /> bl PrintWord<br />#endif<br /><br />#if 1<br /> mov r1, #GPIO_CTL_BASE<br /> add r1, r1, #oGPIO_F<br /> mov r2, #0x70<br /> str r2, [r1, #oGPIO_DAT]<br />#endif<br /><br /> mov pc, r10<br /><br />@ clear memory<br />@ r0: start address<br />@ r1: length<br />mem_clear:<br /> mov r2, #0<br /> mov r3, r2<br /> mov r4, r2<br /> mov r5, r2<br /> mov r6, r2<br /> mov r7, r2<br /> mov r8, r2<br /> mov r9, r2<br /><br />clear_loop:<br /> stmia r0!, {r2-r9}<br /> subs r1, r1, #(8 * 4)<br /> bne clear_loop<br /><br /> mov pc, lr<br /><br />#endif @ CONFIG_S3C2440_NAND_BOOT<br /><br /><br />@ Initialize UART<br />@<br />@ r0 = number of UART port<br />InitUART:<br /> ldr r1, SerBase<br /> mov r2, #0x0<br /> str r2, [r1, #oUFCON]<br /> str r2, [r1, #oUMCON]<br /> mov r2, #0x3<br /> str r2, [r1, #oULCON]<br /> ldr r2, =0x245<br /> str r2, [r1, #oUCON]<br />#define UART_BRD ((UART_PCLK / (UART_BAUD_RATE * 16)) - 1)<br /> mov r2, #UART_BRD<br /> str r2, [r1, #oUBRDIV]<br /><br /> mov r3, #100<br /> mov r2, #0x0<br />1: sub r3, r3, #0x1<br /> tst r2, r3<br /> bne 1b<br /><br />#if 0<br /> mov r2, #'U'<br /> str r2, [r1, #oUTXHL]<br /><br />1: ldr r3, [r1, #oUTRSTAT]<br /> and r3, r3, #UTRSTAT_TX_EMPTY<br /> tst r3, #UTRSTAT_TX_EMPTY<br /> bne 1b <br /><br /> mov r2, #'0'<br /> str r2, [r1, #oUTXHL]<br /><br />1: ldr r3, [r1, #oUTRSTAT]<br /> and r3, r3, #UTRSTAT_TX_EMPTY<br /> tst r3, #UTRSTAT_TX_EMPTY<br /> bne 1b <br />#endif<br /><br /> mov pc, lr<br /><br /><br />@<br />@ Exception handling functions<br />@<br />HandleUndef:<br />#ifdef CONFIG_DEBUG_LL<br /> mov r12, r14<br /> ldr r0, STR_UNDEF<br /> ldr r1, SerBase<br /> bl PrintWord<br /> bl PrintFaultAddr<br />#endif<br />1: b 1b @ infinite loop<br /><br />HandleSWI:<br />#ifdef CONFIG_DEBUG_LL<br /> mov r12, r14<br /> ldr r0, STR_SWI<br /> ldr r1, SerBase<br /> bl PrintWord<br /> bl PrintFaultAddr<br />#endif<br />1: b 1b @ infinite loop<br /><br />HandlePrefetchAbort:<br />#ifdef CONFIG_DEBUG_LL<br /> mov r12, r14<br /> ldr r0, STR_PREFETCH_ABORT<br /> ldr r1, SerBase<br /> bl PrintWord<br /> bl PrintFaultAddr<br />#endif<br />1: b 1b @ infinite loop<br /><br />HandleDataAbort:<br />#ifdef CONFIG_DEBUG_LL<br /> mov r12, r14<br /> ldr r0, STR_DATA_ABORT<br /> ldr r1, SerBase<br /> bl PrintWord<br /> bl PrintFaultAddr<br />#endif<br />1: b 1b @ infinite loop<br /><br />HandleIRQ:<br />#ifdef CONFIG_DEBUG_LL<br /> mov r12, r14<br /> ldr r0, STR_IRQ<br /> ldr r1, SerBase<br /> bl PrintWord<br /> bl PrintFaultAddr<br />#endif<br />1: b 1b @ infinite loop<br /><br />HandleFIQ:<br />#ifdef CONFIG_DEBUG_LL<br /> mov r12, r14<br /> ldr r0, STR_FIQ<br /> ldr r1, SerBase<br /> bl PrintWord<br /> bl PrintFaultAddr<br />#endif<br />1: b 1b @ infinite loop<br /><br />HandleNotUsed:<br />#ifdef CONFIG_DEBUG_LL<br /> mov r12, r14<br /> ldr r0, STR_NOT_USED<br /> ldr r1, SerBase<br /> bl PrintWord<br /> bl PrintFaultAddr<br />#endif<br />1: b 1b @ infinite loop<br /><br /><br />@<br />@ Low Level Debug<br />@<br />#ifdef CONFIG_DEBUG_LL<br /><br />@<br />@ PrintFaultAddr: Print falut address<br />@<br />@ r12: contains address of instruction + 4<br />@<br />PrintFaultAddr:<br /> mov r0, r12 @ Print address of instruction + 4<br /> ldr r1, SerBase<br /> bl PrintHexWord<br /> mrc p15, 0, r0, c6, c0, 0 @ Read fault virtual address<br /> ldr r1, SerBase<br /> bl PrintHexWord<br /> mov pc, lr<br /><br />@ PrintHexNibble : prints the least-significant nibble in R0 as a<br />@ hex digit<br />@ r0 contains nibble to write as Hex<br />@ r1 contains base of serial port<br />@ writes ro with XXX, modifies r0,r1,r2<br />@ TODO : write ro with XXX reg to error handling<br />@ Falls through to PrintChar<br />PrintHexNibble:<br /> adr r2, HEX_TO_ASCII_TABLE<br /> and r0, r0, #0xF<br /> ldr r0, [r2, r0] @ convert to ascii<br /> b PrintChar<br /><br />@ PrintChar : prints the character in R0<br />@ r0 contains the character<br />@ r1 contains base of serial port<br />@ writes ro with XXX, modifies r0,r1,r2<br />@ TODO : write ro with XXX reg to error handling<br />PrintChar:<br />TXBusy:<br /> ldr r2, [r1, #oUTRSTAT]<br /> and r2, r2, #UTRSTAT_TX_EMPTY<br /> tst r2, #UTRSTAT_TX_EMPTY<br /> beq TXBusy <br /> str r0, [r1, #oUTXHL]<br /> mov pc, lr<br /><br />@ PrintWord : prints the 4 characters in R0<br />@ r0 contains the binary word<br />@ r1 contains the base of the serial port<br />@ writes ro with XXX, modifies r0,r1,r2<br />@ TODO : write ro with XXX reg to error handling<br />PrintWord:<br /> mov r3, r0<br /> mov r4, lr<br /> bl PrintChar<br /><br /> mov r0, r3, LSR #8 /* shift word right 8 bits */<br /> bl PrintChar<br /><br /> mov r0, r3, LSR #16 /* shift word right 16 bits */<br /> bl PrintChar<br /> <br /> mov r0, r3, LSR #24 /* shift word right 24 bits */<br /> bl PrintChar<br /><br /> mov r0, #'\r'<br /> bl PrintChar<br /><br /> mov r0, #'\n'<br /> bl PrintChar<br /><br /> mov pc, r4<br /><br />@ PrintHexWord : prints the 4 bytes in R0 as 8 hex ascii characters<br />@ followed by a newline<br />@ r0 contains the binary word<br />@ r1 contains the base of the serial port<br />@ writes ro with XXX, modifies r0,r1,r2<br />@ TODO : write ro with XXX reg to error handling<br />PrintHexWord:<br /> mov r4, lr<br /> mov r3, r0<br /> mov r0, r3, LSR #28<br /> bl PrintHexNibble<br /> mov r0, r3, LSR #24<br /> bl PrintHexNibble<br /> mov r0, r3, LSR #20<br /> bl PrintHexNibble<br /> mov r0, r3, LSR #16<br /> bl PrintHexNibble<br /> mov r0, r3, LSR #12<br /> bl PrintHexNibble<br /> mov r0, r3, LSR #8<br /> bl PrintHexNibble<br /> mov r0, r3, LSR #4<br /> bl PrintHexNibble<br /> mov r0, r3<br /> bl PrintHexNibble<br /><br /> mov r0, #'\r'<br /> bl PrintChar<br /><br /> mov r0, #'\n'<br /> bl PrintChar<br /><br /> mov pc, r4<br />#endif<br /> <br />@<br />@ Data Area<br />@<br />@ Memory configuration values<br />.align 4<br />mem_cfg_val:<br /> .long vBWSCON<br /> .long vBANKCON0<br /> .long vBANKCON1<br /> .long vBANKCON2<br /> .long vBANKCON3<br /> .long vBANKCON4<br /> .long vBANKCON5<br /> .long vBANKCON6<br /> .long vBANKCON7<br /> .long vREFRESH<br /> .long vBANKSIZE<br /> .long vMRSRB6<br /> .long vMRSRB7<br /><br /><br />@ Processor clock values<br />.align 4<br />clock_locktime:<br /> .long vLOCKTIME<br />@mpll_value:<br />@ .long vMPLLCON_NOW<br />mpll_value_USER:<br /> .long vMPLLCON_NOW_USER<br />clkdivn_value:<br /> .long vCLKDIVN_NOW<br /><br />@ initial values for serial<br />uart_ulcon:<br /> .long vULCON<br />uart_ucon:<br /> .long vUCON<br />uart_ufcon:<br /> .long vUFCON<br />uart_umcon:<br /> .long vUMCON<br />@ inital values for GPIO<br />gpio_con_uart:<br /> .long vGPHCON<br />gpio_up_uart:<br /> .long vGPHUP<br /><br /> .align 2<br />DW_STACK_START:<br /> .word STACK_BASE+STACK_SIZE-4<br /><br />#ifdef CONFIG_DEBUG_LL<br /> .align 2<br />HEX_TO_ASCII_TABLE:<br /> .ascii "0123456789ABCDEF"<br />STR_STACK:<br /> .ascii "STKP"<br />STR_UNDEF:<br /> .ascii "UNDF"<br />STR_SWI:<br /> .ascii "SWI "<br />STR_PREFETCH_ABORT:<br /> .ascii "PABT"<br />STR_DATA_ABORT:<br /> .ascii "DABT"<br />STR_IRQ:<br /> .ascii "IRQ "<br />STR_FIQ:<br /> .ascii "FIQ"<br />STR_NOT_USED:<br /> .ascii "NUSD"<br /> .align 2<br />STR_OK:<br /> .ascii "OK "<br />STR_FAIL:<br /> .ascii "FAIL"<br />STR_CR:<br /> .ascii "\r\n"<br />#endif<br /><br />.align 4<br />SerBase:<br />#if defined(CONFIG_SERIAL_UART0)<br /> .long UART0_CTL_BASE<br />#elif defined(CONFIG_SERIAL_UART1)<br /> .long UART1_CTL_BASE<br />#elif defined(CONFIG_SERIAL_UART2)<br /> .long UART2_CTL_BASE<br />#else<br />#error not defined base address of serial<br />#endif<br /><br />#ifdef CONFIG_PM<br />.align 4<br />PMCTL0_ADDR:<br /> .long 0x4c00000c<br />PMCTL1_ADDR:<br /> .long 0x56000080<br />PMST_ADDR:<br /> .long 0x560000B4<br />PMSR0_ADDR:<br /> .long 0x560000B8<br />REFR_ADDR:<br /> .long 0x48000024<br />#endif<br /> |
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