我在QuartusII下编译以下程序：
-- 工程名称：ADDER_CTRL.qpf
-- 文件名称：ADDER_CTRL.vhd
-- 带控制端口的加法器
-- ┌──────┐
-- in1>──┤ │
-- │ adder ├──> pout
-- in2>──┤ │
-- └──┬───┘
-- cnt1 >────┘
-------------------------------
-- library include
-------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE work.all;
entity adder_ctrl is
port(
in1 : in bit_vector(0 to 3);
in2 : in bit_vector(0 to 3);
cnt1: in bit;
pout: out bit_vector(0 to 3));
end adder_ctrl;
architecture func of adder_ctrl is
begin
process(cnt1)
begin
if(cnt1='1')then
pout <= in1 + in2;
end if;
end process;
end func;
编译时出现以下错误：
Error: VHDL error at adder_ctrl.vhd(34):
can't determine definition of operator ""+"" -- found 0 possible definitions
不知道错在哪里。 |
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