这个模块怎么实现不了vhdl cout输出为不定值

只看该作者 · 2008-6-25 01:36

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl1 is
port(s1:in std_logic_vector(3 downto 0);
    s0:in std_logic_vector(3 downto 0) ;
    min1:in std_logic_vector(3 downto 0);
    min0:in std_logic_vector(3 downto 0);
    cout:out std_logic);
    end vhdl1;
architecture xuan of vhdl1 is
signal m0:std_logic;
signal m1:std_logic;
signal m2:std_logic;
signal m3:std_logic;
begin
p_a:process(min1)
begin
if min1="0101" then m0<='1';
else m0<='0';
end if ;
end process p_a;
p_b:process(min0)
begin
if min0="1001" then m1<='1';
else m1<='0';
end if ;
end process p_b;
p_c:process(s1)
begin
if s1="0101" then m2<='1';
else m2<='0';
end if ;
end process p_c;
p_d:process (s0)
begin
case s0 is
when"0001"=>m3<='1';
when"0011"=>m3<='1';
when"0101"=>m3<='1';
when"0111"=>m3<='1';
when others=>m3<='0';
end case;
end process p_d;
p_e:process(m0,m1,m2,m3)
    begin
    if m0='1' and m1='1' and m2='1' and m3='1' then
    cout<='1';
    else cout<='0';
    end if ;
    end process p_e;
end xuan;