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library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_arith.all;<br />use ieee.std_logic_unsigned.all;<br />entity ram0 is <br />port( clk :in std_logic;<br /> reset :in std_logic; <br /> q1_1 :out std_logic_vector(7 downto 0); <br /> q2_2 :out std_logic_vector(7 downto 0); <br /> data1_1:out std_logic_vector(7 downto 0);<br /> data2_2:out std_logic_vector(7 downto 0);<br /> wraddress1_1:out std_logic_vector(3 downto 0);<br /> datain :in std_logic_vector(7 downto 0);<br /> dataout:out std_logic_vector(7 downto 0)<br />);<br />end ram0;<br />--********************************************************<br />architecture behave of ram0 is<br />signal data1 : std_logic_vector(7 downto 0);<br />signal data2 : std_logic_vector(7 downto 0);<br /><br />signal q1 : std_logic_vector(7 downto 0);<br />signal q2 : std_logic_vector(7 downto 0);<br /><br />signal wren1 : std_logic;<br />signal wraddress1 : std_logic_vector(3 downto 0);<br />signal rden1 : std_logic;<br />signal rdaddress1 : std_logic_vector(3 downto 0);<br />signal wren2 : std_logic;<br />signal wraddress2 : std_logic_vector(3 downto 0);<br />signal rden2 : std_logic;<br />signal rdaddress2 : std_logic_vector(3 downto 0);<br /><br /><br /><br /><br />component ram1<br /> PORT<br /> (<br /> data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);<br /> wren : IN STD_LOGIC;<br /> wraddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0);<br /> rdaddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0);<br /> rden : IN STD_LOGIC;<br /> clock : IN STD_LOGIC;<br /> q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)<br /> );<br />end component;<br />component ram2<br /> PORT<br /> (<br /> data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);<br /> wren : IN STD_LOGIC;<br /> wraddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0);<br /> rdaddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0);<br /> rden : IN STD_LOGIC;<br /> clock : IN STD_LOGIC;<br /> q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)<br /> );<br />end component;<br />--*********************************************************<br />begin<br />q1_1<=q1;<br />q2_2<=q2;<br />data1_1<=data1;<br />data2_2<=data2;<br />wraddress1_1<= wraddress1;<br /><br />ram1_inst : ram1 PORT MAP <br />( data =>data1,<br /> wren => wren1,<br /> wraddress=> wraddress1,<br /> rdaddress=> rdaddress1,<br /> rden => rden1,<br /> clock => clk,<br /> q => q1<br /> );<br />ram2_inst : ram2 PORT MAP (<br /> data => data2,<br /> wren => wren2,<br /> wraddress=> wraddress2,<br /> rdaddress=> rdaddress2,<br /> rden => rden2,<br /> clock => clk,<br /> q => q2<br /> );<br /> <br />u1:process(reset,clk)<br />begin<br /> if(reset='0')then<br /> wraddress1<="0000";<br /> elsif(clk'event and clk='1')then<br /> wren1<='1';<br /> wraddress1<=wraddress1+1;<br /> if wraddress1<="0000" then<br /> data1<=datain;<br /> elsif wraddress1="0001" then <br /> data1<=datain;<br /> elsif wraddress1="0010" then <br /> data1<=datain;<br /> elsif wraddress1="0011" then <br /> data1<=datain;<br /> elsif wraddress1="0100" then <br /> data1<=datain;<br /> elsif wraddress1="0101" then <br /> data1<=datain;<br /> elsif wraddress1="0110" then <br /> data1<=datain;<br /> elsif wraddress1="0111" then <br /> data1<=datain;<br /> elsif wraddress1="1000" then <br /> data1<=datain;<br /> elsif wraddress1="1001" then <br /> data1<=datain;<br /> elsif wraddress1="1010" then <br /> data1<=datain;<br /> elsif wraddress1="1011" then <br /> data1<=datain;<br /> elsif wraddress1="1100" then <br /> data1<=datain; <br /> elsif wraddress1="1101" then <br /> data1<=datain; <br /> elsif wraddress1="1110" then <br /> data1<=datain; <br /> elsif wraddress1="1111" then <br /> data1<=datain; <br /> end if;<br /> end if; <br />end process; <br />--******************************************************* <br />u2:process(reset,clk) <br /> begin<br /> if (reset<='0') then<br /> wraddress2<="0000";<br /> elsif (clk'event and clk='1') then<br /> wren2<='1'; <br /> wraddress2<=wraddress2+1;<br /> if wraddress2="0000" then<br /> data2<=q1;<br /> elsif wraddress2="0001" then <br /> data2<=q1;<br /> elsif wraddress2="0010" then <br /> data2<=q1;<br /> elsif wraddress2="0011" then <br /> data2<=q1;<br /> elsif wraddress2="0100" then <br /> data2<=q1;<br /> elsif wraddress2="0101" then <br /> data2<=q1;<br /> elsif wraddress2="0110" then <br /> data2<=q1;<br /> elsif wraddress2="0111" then <br /> data2<=q1;<br /> elsif wraddress2="1000" then <br /> data2<=q1;<br /> elsif wraddress2="1001" then <br /> data2<=q1;<br /> elsif wraddress2="1010" then <br /> data2<=q1;<br /> elsif wraddress2="1011" then <br /> data2<=q1;<br /> elsif wraddress2="1100" then <br /> data2<=q1; <br /> elsif wraddress2="1101" then <br /> data2<=q1; <br /> elsif wraddress2="1110" then <br /> data2<=q1; <br /> elsif wraddress2="1111" then <br /> data2<=q1; <br /> end if;<br /> end if; <br />end process; <br />--********************************************************<br />u3:process(clk,reset)<br /> begin<br /> if reset<='0' then<br /> rdaddress2<="0000";<br /> elsif (clk'event and clk='1') then<br /> rden2<='1';<br /> rdaddress2<=rdaddress2+1; <br /> if rdaddress2="0000" then<br /> dataout<=q2;<br /> elsif rdaddress2="0001" then <br /> dataout<=q2;<br /> elsif rdaddress2="0010" then <br /> dataout<=q2;<br /> elsif rdaddress2="0011" then <br /> dataout<=q2;<br /> elsif rdaddress2="0100" then <br /> dataout<=q2;<br /> elsif rdaddress2="0101" then <br /> dataout<=q2;<br /> elsif rdaddress2="0110" then <br /> dataout<=q2;<br /> elsif rdaddress2="0111" then <br /> dataout<=q2;<br /> elsif rdaddress2="1000" then <br /> dataout<=q2;<br /> elsif rdaddress2="1001" then <br /> dataout<=q2;<br /> elsif rdaddress2="1010" then <br /> dataout<=q2;<br /> elsif rdaddress2="1011" then <br /> dataout<=q2;<br /> elsif rdaddress2="1100" then <br /> dataout<=q2;<br /> elsif rdaddress2="1101" then <br /> dataout<=q2;<br /> elsif rdaddress2="1110" then <br /> dataout<=q2;<br /> elsif rdaddress2="1111" then <br /> dataout<=q2;<br /> end if;<br /> end if;<br /><br />end process; <br />end behave;<br /><br /><br /><br /><br /><br /><br /><br /> <br /> |
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