我调试串口模块的发送端，让他一直发送一个常数，为什么接受不到啊？
我的时钟周期已经设置为1/9600(=104us).没有校验位。我已经弄了好几天了还是没有结果。刚刚学verilog，跪求高人指点。谢谢
module transfer(clk,rst/*,send_enable*/,txd,send_over/*,send_bus*/);
input clk,rst/*,send_enable*/;
//input[7:0] send_bus;
output txd,send_over;
reg txd;
reg send_over;//when finish sending,set send_over to 1,otherwise send_over is 0
wire[7:0] send_bus;
wire send_enable;
parameter[2:0] IDLE=3'B001;
parameter[2:0] SEND=3'B010;
parameter[2:0] STOP=3'B100;
reg[2:0] state;
reg[2:0] count;
reg[7:0] buffer;
assign send_bus=8'b01010101;//为了测试，我把总线上放固定的常数，希望接受到这个常数。
assign send_enable=1'b1;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
state<=IDLE;
count<=0;
send_over<=0;
buffer<=8'b0;
txd<=1;
end
else
begin
case(state)
IDLE:
begin
if(send_enable)
begin
txd<=0;
state<=SEND;
end
else
begin
state<=IDLE;
txd<=1;
end
buffer<=send_bus;
count<=0;
send_over<=0;
end
SEND:
begin
txd<=buffer[count];
if(count==7)
begin
count<=0;
state<=STOP;
end
else
begin
count<=count+1;
state<=SEND;
end
end
STOP:
begin
txd<=1;
state<=IDLE;
send_over<=1;
end
default:
begin
state<=IDLE;
txd<=1;
send_over<=0;
end
endcase
end
end
endmodule
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