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我调试串口模块的发送端，让他一直发送一个常数，为什么接受不到啊？<br />我的时钟周期已经设置为1/9600(=104us).没有校验位。我已经弄了好几天了还是没有结果。刚刚学verilog，跪求高人指点。谢谢<br />module transfer(clk,rst/*,send_enable*/,txd,send_over/*,send_bus*/);<br />input clk,rst/*,send_enable*/;<br />//input[7:0] send_bus;<br />output txd,send_over;<br />reg txd;<br />reg send_over;//when finish sending,set send_over to 1,otherwise send_over is 0<br />wire[7:0] send_bus;<br />wire send_enable;<br />parameter[2:0] IDLE=3'B001;<br />parameter[2:0] SEND=3'B010;<br />parameter[2:0] STOP=3'B100;<br /><br />reg[2:0] state;<br />reg[2:0] count;<br />reg[7:0] buffer;<br />assign send_bus=8'b01010101;//为了测试，我把总线上放固定的常数，希望接受到这个常数。<br />assign send_enable=1'b1;<br /><br />always @(posedge clk or negedge rst)<br />begin<br /> if(!rst)<br /> begin<br /> state<=IDLE;<br /> count<=0;<br /> send_over<=0;<br /> buffer<=8'b0;<br /> txd<=1;<br /> end<br /> else<br /> begin<br /> case(state)<br /> IDLE:<br /> begin<br /> if(send_enable) <br /> begin<br /> txd<=0;<br /> state<=SEND;<br /> end<br /> else<br /> begin<br /> state<=IDLE;<br /> txd<=1; <br /> end<br /> buffer<=send_bus;<br /> count<=0;<br /> send_over<=0;<br /> end<br /> SEND:<br /> begin<br /> txd<=buffer[count];<br /> if(count==7)<br /> begin<br /> count<=0;<br /> state<=STOP;<br /> end<br /> else<br /> begin<br /> count<=count+1;<br /> state<=SEND;<br /> end<br /> end<br /> STOP:<br /> begin<br /> txd<=1;<br /> state<=IDLE;<br /> send_over<=1;<br /> end<br /> default:<br /> begin<br /> state<=IDLE;<br /> txd<=1;<br /> send_over<=0;<br /> end<br /> endcase<br /> end<br />end<br /><br />endmodule<br /> |
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