library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test1 is
port( clk :in std_logic;
sense :in std_logic_vector(2 downto 0);
moto11 :out std_logic;
moto12 :out std_logic;
moto21 :out std_logic;
moto22 :out std_logic
);
end;
architecture one of test1 is
signal sm_cnt :integer range 0 to 16000-1;
signal cnt1 :integer range 0 to 16000;
signal scan_clk :std_logic;
signal scan :integer range 0 to 100 ;
signal scan1 :integer range 0 to 100 ;
-------------------------------------------------------
begin
------------------------------------------------------------
------------------------------------------------------------
process(clk)
begin
if clk'event and clk='1' then
if sm_cnt=16000-1 then sm_cnt<=0;
else sm_cnt<=sm_cnt+1;
end if;
end if;
end process;
moto11<='1' when sm_cnt<scan else
'0';
---------------------------------------
process(clk)
begin
if clk'event and clk='1' then
if cnt1=16000-1 then cnt1<=0;
else cnt1<=cnt1+1;
end if;
end if;
end process;
moto21<='1' when cnt1<scan1 else
'0';
----------------------------------
process(sense)
begin
scan1<=10;
case sense is
when "000" => scan<=0;
when "001" => scan<=10;
when "010" => scan<=40;
when "011" => scan<=10;
when "100" => scan<=80;
when "110" => scan<=80;
when others=> scan<=10;
end case;
end process;
moto12<='0';moto22<='0';
end;
只能有停和全速转动状态 请高手帮忙看下 急！！！
谢谢！！ |
楼主
标题置顶
标题高亮
