我是个CPLD的新手，用maxplus写了一个计数器小程序。代码如下：
Timertest.vhd
library ieee;
use ieee.std_logic_1164.all;
ENTITY TimerTest IS
PORT(
Reset : in std_logic;
Clk : in std_logic;
nWR : in std_logic;
Data : in std_logic_vector(7 downto 0);
Tout : out std_logic
);
END TimerTest ;
ARCHITECTURE a OF TimerTest IS
signal TSet: std_logic_vector(7 downto 0);
signal EnClk: std_logic;
COMPONENT TimerSet
PORT(
Reset : in std_logic;
Data : in std_logic_vector(7 downto 0);
nWR : in std_logic;
EnClk : out std_logic
);
END COMPONENT;
COMPONENT Timer
port(
Reset : in std_logic;
Clk : in std_logic;
Tout : out std_logic;
EnClk : in std_logic
);
end component;
begin
myTimer :Timer
port map (
Reset => Reset,
Clk => Clk,
Tout => Tout,
EnClk => EnClk,
);
myTimerSet: TimerSet
port map(
Reset => Reset,
Data => Data,
nWR => nWR,
EnClk => EnClk,
);
END a;
Timer.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY Timer IS
port(
Reset : in std_logic;
Clk : in std_logic;
Tout : out std_logic;
EnClk : in std_logic
);
END Timer;
ARCHITECTURE a OF Timer IS
signal TCounter :std_logic_vector(7 downto 0);
signal TT :std_logic;
BEGIN
Tout<=TT;
process(Clk)
begin
if(Reset='0') then
TCounter<=X"1f";
TT<='1';
elsif rising_edge(Clk) then
if(EnClk='1') then
if(TCounter=X"00") then
TCounter <=X"1f";
TT <= not TT;
else
TCounter <= TCounter - 1;
end if;
end if;
end if;
end process;
END a;
TimerSet.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY TimerSet IS
PORT(
Reset : in std_logic;
Data : in std_logic_vector(7 downto 0);
nWR : in std_logic;
EnClk : out std_logic
);
END TimerSet;
ARCHITECTURE a OF TimerSet IS
BEGIN
process(Reset,nWR,Data)
begin
if(Reset='0')then
EnClk <='0';
elsif(nWR='0') then
EnClk <='1';
end if;
end process;
END a;
仿真的结果Tout是正确的。
可是察看 TCounter 的值变化是不规律的。
请各位高人 给与指点。 谢谢！![]() |
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