我想实现图那样的时序,就是在IN_CPLDCS信号低电平的时候,检测32个输入信号IN_INSIGNAL[31..0],如果输入信号出现过1就保存下来。在IN_CPLDCS信号高电平时,分组把32个信号读出数据8位端口。具体就是IN_CPLDCS信号高电平时,当IN_RD第一个高电平时输出IN_INSIGNAL[31..0]中的高8位;当IN_RD第二个高电平时输出IN_INSIGNAL[31..0]中的另外8位,如此类推。 IN_RD的4个高电平后就读完了。 我用VHDL语言使用状态机的方法,来做,但是综合后,竟然用了300多个宏单元!! 我想这样的功能应该不用这么多把?是不是我写得程序不好?请大家指教! 程序如下: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_arith.ALL;
ENTITY dslammain IS PORT( IN_CPLDCS, IN_RD: IN STD_LOGIC; IN_SIGNAL: IN STD_LOGIC_VECTOR(31 downto 0); IN_GCLK: IN STD_LOGIC; OUT_DATA : OUT STD_LOGIC_VECTOR(7 downto 0); );
END dslammain ;
ARCHITECTURE behav OF dslammain IS
TYPE STATE IS (WAITTING,TSTSIGNAL,DATAOUT); SIGNAL CURR_STATE: STATE; SIGNAL REG_DATA: STD_LOGIC_VECTOR(31 downto 0);
BEGIN
-- Process Statement testsignal: PROCESS (IN_GCLK) VARIABLE cnt4rd: integer range 5 downto 0;
VARIABLE rd_start: bit;
BEGIN
IF RISING_EDGE(IN_GCLK) THEN
CASE CURR_STATE IS WHEN WAITTING=> REG_DATA<="00000000000000000000000000000000"; IF IN_CPLDCS='0' THEN CURR_STATE<=TSTSIGNAL; END IF; WHEN TSTSIGNAL=> FOR i IN 31 DOWNTO 0 LOOP IF(IN_SIGNAL(i)='1') THEN REG_DATA(i)<='1'; --REG_DATA(i):='1'; END IF; END LOOP; IF IN_CPLDCS='1' THEN CURR_STATE<=DATAOUT; END IF;
WHEN DATAOUT=> IF(IN_RD='1') THEN rd_start:='1';
ELSIF(IN_RD='0' AND rd_start='1') THEN cnt4rd:=cnt4rd+1; rd_start:='0'; END IF;
IF(rd_start='1')THEN IF(cnt4rd=0)THEN OUT_DATA(7)<=REG_DATA(31); OUT_DATA(6)<=REG_DATA(30); OUT_DATA(5)<=REG_DATA(29); OUT_DATA(4)<=REG_DATA(28); OUT_DATA(3)<=REG_DATA(27); OUT_DATA(2)<=REG_DATA(26); OUT_DATA(1)<=REG_DATA(25); OUT_DATA(0)<=REG_DATA(24);
ELSIF(cnt4rd=1)THEN OUT_DATA(7)<=REG_DATA(23); OUT_DATA(6)<=REG_DATA(22); OUT_DATA(5)<=REG_DATA(21); OUT_DATA(4)<=REG_DATA(20); OUT_DATA(3)<=REG_DATA(19); OUT_DATA(2)<=REG_DATA(18); OUT_DATA(1)<=REG_DATA(17); OUT_DATA(0)<=REG_DATA(16);
ELSIF(cnt4rd=2)THEN OUT_DATA(7)<=REG_DATA(15); OUT_DATA(6)<=REG_DATA(14); OUT_DATA(5)<=REG_DATA(13); OUT_DATA(4)<=REG_DATA(12); OUT_DATA(3)<=REG_DATA(11); OUT_DATA(2)<=REG_DATA(10); OUT_DATA(1)<=REG_DATA(9); OUT_DATA(0)<=REG_DATA(8);
ELSIF(cnt4rd=3)THEN OUT_DATA(7)<=REG_DATA(7); OUT_DATA(6)<=REG_DATA(6); OUT_DATA(5)<=REG_DATA(5); OUT_DATA(4)<=REG_DATA(4); OUT_DATA(3)<=REG_DATA(3); OUT_DATA(2)<=REG_DATA(2); OUT_DATA(1)<=REG_DATA(1); OUT_DATA(0)<=REG_DATA(0); END IF;
END IF; IF (cnt4rd=4) THEN CURR_STATE<=WAITTING; END IF;
WHEN OTHERS => NULL; END CASE; END IF; END PROCESS testsignal; END behav; |