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用<br />estimate_test_coverage<br />结果<br />Loading target library 'slow'<br /> Loading design ...<br /> Using test protocol in memory.<br /> Starting test coverage estimation ...<br />Error: Can not get fault coverage for design PPM_TOP due to design rule checking error.<br />然后check_dft<br />**************************************************<br /> Test Design Rule Violation Summary<br /><br /> Total violations: 69<br />**************************************************<br /><br />PROTOCOL VIOLATIONS<br /> 35 Asynchronous pins uncontrollable violations (TEST-116)<br /> 15 Asynchronous signal active during scan violations (TEST-280)<br />SCAN IN VIOLATIONS<br /> 15 Cell constant during scan violations (TEST-142)<br /> 1 Cell is uncontrollable during scan violation (TEST-302)<br />CAPTURE VIOLATIONS<br /> 2 Unreliable capture (async pin) violations (TEST-471)<br /> 1 Cell does not capture violation (TEST-310)<br /><br /><br />**************************************************<br /> Sequential Cell Summary<br /><br /> 43 out of 1179 sequential cells have violations<br />**************************************************<br /><br />简单描述下设计，异步复位，一个全局时钟，内部有复位逻辑，是同步的。<br />我列举几个DRC违例，想请问下如何解决，DFT我是第一次作。每类问题我列一个出来问，请教下如何解决，详细的DRC警告见附件：<br />1.Warning: Cell uart_top1/tx232/m1_state_reg_1_0 (SDFFNRX1) is always asynchronously set/cleared. (TEST-280)<br />2.Warning: Asynchronous pins of cell uart_top1/tx232/data_in_waiting_reg_0_0 (SDFFNSRX2) are uncontrollable. (TEST-116)<br />3.Warning: Sequential cell uart_top1/tx232/q_reg_1_0 (SDFFNSX1) has constant logic 1/0 state. (TEST-142)<br />4.Warning: Cell gen_sclk1/Phase_cnt_reg_0_0 (SDFFNSRX4) is not scan controllable. (TEST-302)<br />5.Warning:Asynchronous control pin SN of cellgen_sclk1/Phase_cnt_reg_0_0(SDFFNSRX4) can change in the capture cycle.This can cause the cell tocapture unreliably. (TEST-471)<br />6.Warning: Data can not be captured into cell gen_sclk1/Phase_cnt_reg_0_0 (SDFFNSRX4). (TEST-310)<br /> ...binding scan-out state... |
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