该设计主要完成数据锁存和并行转串行的功能 顶层模块为YBK 其中主要包含4种模块
MCLK1 MCLK2为时钟分频模块 功能基本类似 MCC1 MCC2 LATCH1 LATCH2为一16位锁存器 其中LATCH1为上升沿触发 LATCH2为下降沿触发 D1 D2为LATCH1类型 D3 D4 为LATCH2类型 SHIFT为一锁存加移位寄存器 UD1UD2UD3UD4为该类型寄存器
这里主要讨论C0 C1 和 DIN 输出 TMP_R1 TMP_G1 TMP_R2 TMP_G2 一般我的输入 波形会如下 ___ ____ ____________________ | | | | | | | | C0 |____| |____| ____ | | | | C1_ ____________________| |_____________
DIN__/R1\_/G1\_/R2\_/G2\____________________ (16b)\__/ \__/ \__/ \__/
C0的下降沿 会触发D3D4 锁存R1 R2
C0的上升沿 会触发D1D2 锁存G1 G2
在C1的上升沿 MCC1 MCC2的计数被启动 MCC2产生16个正脉冲DCLK MCC1产生32个正脉冲pclk 通过触发产生Q Q的相位与dclk延迟180度
DCLK连接到UD1UD2UD3UD4
通过dclk串行输出4路 16bit的串行数据
症状:输入为全零时 TMP_R1 有时会被误触发成1
请大虾们分析一下
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity LATCH1 is port( din :in std_logic_vector(15 downto 0); dout :out std_logic_vector(15 downto 0); store :in std_logic ); end LATCH1; architecture LATCH1 of LATCH1 is signal tmp: std_logic_vector(15 downto 0); begin
process(store) begin if(store'event and store='1')then tmp<=dIN; end if; end process; dout<=tmp; end Latch1;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity LATCH2 is port( din :in std_logic_vector(15 downto 0); dout :out std_logic_vector(15 downto 0); store :in std_logic ); end LATCH2; architecture LATCH2 of LATCH2 is signal tmp: std_logic_vector(15 downto 0); begin
process(store) begin if(store'event and store='0')then tmp<=dIN; end if; end process; dout<=tmp; end Latch2;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity mclk is port( clkin :in std_logic; quickclk :in std_logic; count :out std_logic_vector(5 downto 0); pclk :out std_logic ); end mclk; architecture mclk of mclk is signal count_tmp: std_logic_vector(5 downto 0); signal flag:std_logic;
begin ----------------------- count<=count_tmp; ----------------------- process(quickclk,clkin,count_tmp) begin if clkin='1' then if count_tmp<37 then if quickclk'event and quickclk='1' then count_tmp<=count_tmp+1; if count_tmp>4 then flag<='1'; end if; end if; elsif quickclk='0' then flag<='0'; end if; elsif clkin='0' then count_tmp<="000000"; flag<='0'; end if; end process; ----------------------- --clkout<=quickclk when (count_tmp<4 and clkin='1') else '0'; -- pclk<=count_tmp(0) when flag='1' else '0'; pclk<=quickclk when flag='1' else '0'; ----------------------- end mclk; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity mclk1 is port( clkin :in std_logic; quickclk :in std_logic; count :out std_logic_vector(5 downto 0); pclk :out std_logic ); end mclk1;
architecture mclk1 of mclk1 is signal count_tmp: std_logic_vector(5 downto 0); signal flag:std_logic;
begin ----------------------- count<=count_tmp; ----------------------- process(quickclk,clkin,count_tmp) begin if clkin='1' then if count_tmp<36 then if quickclk'event and quickclk='1' then count_tmp<=count_tmp+1; if count_tmp>3 then flag<='1'; end if; end if; elsif quickclk='0' then flag<='0'; end if; elsif clkin='0' then count_tmp<="000000"; flag<='0'; end if; end process; ----------------------- --clkout<=quickclk when (count_tmp<4 and clkin='1') else '0'; -- pclk<=quickclk when flag='1' else '0'; pclk<=count_tmp(0) when flag='1' else '0'; ----------------------- end mclk1;
--16bit shiftreg 并行到串行转换 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity shift is port( dIN :in std_logic_vector(15 downto 0); count :in std_logic_vector(5 downto 0); -- CLKIN :in std_logic; pCLk :in std_logic; quickclk :in std_logic; sout :out std_logic ); end shift;
architecture rtl of shift is signal tmp :std_logic_vector(16 downto 0);-- begin PROCESS(COUNT,pclk,quickclk) BEGIN if(count="000010") then tmp(15 downto 0)<=din; else --if(count(0)'event and count(0)='1') then if(pclk='1') then if(quickclk'event and quickclk='0') then tmp<=tmp(15 downto 0) & '0' ; end if; end if; end if; END PROCESS; sout<=tmp(16); end rtl; --16bit shiftreg 并行到串行转换
--clk assign LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLKASSIGN IS PORT( -- OE_C,STR_C STR,OE, ,A,B,C,D :IN STD_LOGIC; CLK :IN STD_LOGIC; S :IN STD_LOGIC_VECTOR(2 DOWNTO
0); -- CLK_2 :OUT STD_LOGIC;-- -- SOE,SSTRSA,SB,SC,SD, :OUT STD_LOGIC;--,CLK_2 SCLK :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END CLKASSIGN;
ARCHITECTURE CLKASSIGN OF CLKASSIGN IS SIGNAL SCLK_B :STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL TMP_SOE,TMP_SSTR :STD_LOGIC; SIGNAL COUNTER :STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
SCLK(0)<=SCLK_B(0) AND ((CLK)); SCLK(1)<=SCLK_B(1) AND ((CLK)); SCLK(2)<=SCLK_B(2) AND ((CLK)); SCLK(3)<=SCLK_B(3) AND ((CLK)); SCLK(4)<=SCLK_B(4) AND ((CLK)); SCLK(5)<=SCLK_B(5) AND ((CLK)); SCLK(6)<=SCLK_B(6) AND ((CLK)); SCLK(7)<=SCLK_B(7) AND ((CLK));
PROCESS(S) BEGIN CASE S IS WHEN "000"=> SCLK_B<=(0=>'1',OTHERS=>'0'); WHEN "001"=> SCLK_B<=(1=>'1',OTHERS=>'0'); WHEN "010"=> SCLK_B<=(2=>'1',OTHERS=>'0'); WHEN "011"=> SCLK_B<=(3=>'1',OTHERS=>'0'); WHEN "100"=> SCLK_B<=(4=>'1',OTHERS=>'0'); WHEN "101"=> SCLK_B<=(5=>'1',OTHERS=>'0'); WHEN "110"=> SCLK_B<=(6=>'1',OTHERS=>'0'); WHEN "111"=> SCLK_B<=(7=>'1',OTHERS=>'0');
WHEN OTHERS=> NULL; END CASE; END PROCESS;
-- CLK_2<=COUNTER(0); -- PROCESS(CLK) -- BEGIN -- IF(CLK'EVENT AND CLK='1')THEN -- COUNTER(1 DOWNTO 0)<=COUNTER(1 DOWNTO 0)+1; -- END IF; -- END PROCESS;
END CLKASSIGN;
--YBK VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY YBK IS PORT( OE_C,STR_C :IN STD_LOGIC; C :IN
STD_LOGIC_VECTOR(1 DOWNTO 0); clkout :out STD_logic; STR,OE :IN STD_LOGIC;--
-,CLK,A,B,C,D,LATCH,LOAD S :IN
STD_LOGIC_VECTOR(2 DOWNTO 0); S3 :IN STD_LOGIC; SS3,B_SS3 :OUT STD_LOGIC;--
SA,SB,SC,SD, DIN :IN
STD_LOGIC_VECTOR(15 DOWNTO 0); QUICKCLK :IN STD_LOGIC;--,CLKIN
R485_232,DATA_C :IN STD_LOGIC; TXD,RXD232,RXD485 :IN STD_LOGIC; RXD,TXD485,TXD232 :OUT STD_LOGIC; SOE,SSTR :OUT STD_LOGIC;--
SA,SB,SC,SD, RD1,RD2,GD1,GD2 :OUT STD_LOGIC; WORKING,TRANSFER :OUT STD_LOGIC; --PWM :IN STD_LOGIC; pclk :buffer std_logic; dclk :buffer std_logic; -- COUNT :buffer std_logic_vector(5 downto
0); SCLK :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END YBK;
ARCHITECTURE YBK OF YBK IS SIGNAL CLK_2,BD :STD_LOGIC; SIGNAL TMP_RD1,TMP_RD2 :STD_LOGIC; SIGNAL TMP_GD1,TMP_GD2 :STD_LOGIC; SIGNAL CLKIN :STD_LOGIC;
--寄存器组
SIGNAL T1,T2,T3,T4 :std_logic_vector(15 downto 0); SIGNAL R1,R2,R3,R4 :std_logic_vector(15 downto 0); SIGNAL COUNT :std_logic_VECTOR(5 DOWNTO 0); SIGNAL CLK :std_logic; --signal pclk : std_logic;
signal Q :std_logic; component MCLK port( clkin :in std_logic; quickclk :in std_logic; count :out std_logic_vector(5 downto 0); pclk :out std_logic ); end component; component MCLK1 port( clkin :in std_logic; quickclk :in std_logic; count :out std_logic_vector(5 downto 0); pclk :out std_logic ); end component; component LATCH1 port( STORE :in std_logic; DIN :IN STD_LOGIC_VECTOR(15 DOWNTO
0); DouT :out STD_LOGIC_VECTOR(15 DOWNTO 0) ); end component;
component LATCH2 port( STORE :in std_logic; DIN :IN STD_LOGIC_VECTOR(15 DOWNTO
0); DouT :out STD_LOGIC_VECTOR(15 DOWNTO 0) ); end component; component SHIFT port( dIN :in std_logic_vector(15 downto 0); sout :out std_logic; pclk :in std_logic; quickclk :in std_logic; count :in std_logic_vector(5 downto 0) ); end component;
component CLKASSIGN port( CLK :IN STD_LOGIC; S :IN STD_LOGIC_VECTOR(2 DOWNTO
0); SCLK :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); end component; BEGIN UD1:SHIFT port map( DIN=>R1, sout=>TMP_RD1, pclk=>dclk,
count=>count,quickclk=>quickclk); UD2:SHIFT port map( DIN=>R2, sout=>TMP_GD1, pclk=>dclk,
count=>count,quickclk=>quickclk); UD3:SHIFT port map( DIN=>R3, sout=>TMP_RD2, pclk=>dclk,
count=>count,quickclk=>quickclk); UD4:SHIFT port map( DIN=>R4, sout=>TMP_GD2, pclk=>dclk,
count=>count,quickclk=>quickclk);
D1:LATCH1 PORT MAP(DIN=>DIN, DOUT=>R4,STORE=>C(0)); D2:LATCH1 PORT MAP(DIN=>R4, DOUT=>R2,STORE=>C(0)); D3:LATCH2 PORT MAP(DIN=>DIN, DOUT=>R3,STORE=>C(0)); D4:LATCH2 PORT MAP(DIN=>R3, DOUT=>R1,STORE=>C(0)); MCC:MCLK port map(CLKIN=>CLKIN,pclk=>pclk, QUICKCLK=>QUICKCLK);
MCC1:MCLK1 port map(CLKIN=>CLKIN,pclk=>dclk, QUICKCLK=>QUICKCLK,count=>count);--
UCLK:CLKASSIGN PORT MAP(CLK=>Q,SCLK=>SCLK,S=>S); --CLK<=quick; CLKOUT<=quickclk; WORKING<=STR; TRANSFER<=TXD; SS3<=S3; B_SS3<=NOT S3; CLKIN<=C(1); PROCESS(pclk,clkin) BEGIN if(clkin='1') then if (pclk'event and pclk='1') then Q<= not Q; end if; else Q<='0'; end if; END PROCESS;
PROCESS(DATA_C) BEGIN IF(DATA_C='1')THEN RD1<=TMP_RD1;--RD1<=not T11(0); -- RD2<=TMP_RD2;--RD2<=not T21(0); -- GD1<=TMP_GD1;--GD1<=not T12(0); -- GD2<=TMP_GD2;--GD2<=not T22(0); -- ELSE RD1<=NOT(TMP_RD1);--RD1<=T11(0); -- RD2<=NOT(TMP_RD2);--RD2<=T21(0); -- GD1<=NOT(TMP_GD1);--GD1<=T12(0); -- GD2<=NOT(TMP_GD2);--GD2<=T22(0); -- END IF; END PROCESS; PROCESS(R485_232) BEGIN IF(R485_232='0')THEN RXD<=RXD485; TXD485<=TXD; ELSE RXD<=RXD232; TXD232<=TXD; END IF; END PROCESS;
PROCESS(OE_C) BEGIN IF(OE_C='0')THEN -- SSTR<=not(STR); SOE<=OE;-- AND PWM; ELSE -- SSTR<=not(STR); SOE<=NOT(OE);-- AND PWM; END IF; END PROCESS;
PROCESS(STR_C) BEGIN IF(STR_C='0')THEN SSTR<=STR; -- SOE<=OE;-- AND PWM; ELSE SSTR<=NOT(STR); -- SOE<=OE;-- AND PWM; END IF; END PROCESS; END YBK;
|
|