我想通过程序实现74ls373的功能! 一下是我编写的程序 library IEEE; use IEEE.std_logic_1164.all;
entity ls74373 is port ( OE ,LE: in std_logic DATA_IN : in std_logic_vector (7 downto 0); DATA_OUT : out std_logic_vector (7 downto 0) ); end ls74373; architecture ls373 of ls74373 is begin process(LE) begin if (OE='0' and LE='1') then DATA_OUT<=DATA_IN; end if; end process; end architecture ls373;
现在遇到的情况是,编译无法通过! 请问是不是我的编程想法上有错误? 我该如何编程实现74ls373呢?
请指教!谢谢! |