有可能是上电时序问题：
建议用示波器抓一下两路电源1.9V 3.3V 那一路先上电。2812芯片上电时序和我们接触的其它芯片有所不同，凭我的经验是3.3V先上电，1.9V后上电（注：浮点处理器28335是内核1.9V先上电）。
对于上电时序，以下这段话摘自tms320f2812数据手册6.9 Power Sequencing Requirements
6.9 Power Sequencing Requirements
TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU,
Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are
some requirements to be met while powering up/powering down the device. The current F2812 silicon
reference schematics (Spectrum Digital Incorporated eZdsp. board) suggests two options for the power
sequencing circuit.
Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp
together. C281x can also be used on boards that have F281x power sequencing implemented; however, if
the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least
1 V.
• Option 1:
In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or
1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG)
modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the
recommended approach.
• Option 2:
Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then
ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins.
1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset
signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules
inside the device. See Figure 6−11 for power-on reset timing.
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