本帖最后由 itelectron 于 2009-8-28 21:59 编辑
/*
* armboot - Startup Code for ARM920 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <status_led.h>
/******************NAND*******/
/*
* Nandflash Boot
*/
//#define STACK_BASE 0x33f00000
//#define STACK_SIZE 0x8000
//#define UBOOT_RAM_BASE 0x33f80000
/* NAND Flash Controller */
//#define NAND_CTL_BASE 0x4E000000
/* Offset */
//#define oNFCONF 0x00
//#define oNFCONT 0x04
//#define oNFCMD 0x08
//#define oNFSTAT 0x20
/******************NAND*******/
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
_TEXT_BASE:
.word TEXT_BASE
.globl _armboot_start
_armboot_start:
.word _start
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
_bss_end:
.word _end
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/*
* the actual start code
*/
start_code:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
bl coloured_LED_init
bl red_LED_on
/* turn off the watchdog */
# define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
ldr r1, =0x7fff
ldr r0, =INTSUBMSK
str r1, [r0]
/* FCLK:HCLK:PCLK = 1:2:4 */
#define LOCKTIME 0x4C000000
#define CAMDIVN 0x4C000018
#define CLKDIVN 0x4C000014
#define CLKDIVN_VAL 0x5 /* UCLK = UPLL/2 */
#define UPLLCON 0x4C000008
#define MPLLCON 0x4C000004
#define MDIV_405 127
#define PDIV_405 2
#define SDIV_405 1
#define MDIV_48 56
#define PDIV_48 2
#define SDIV_48 2
#define vUPLLCON_NOW_USER ((MDIV_48 << 12) | (PDIV_48 << 4) | (SDIV_48))
#define vMPLLCON_NOW_USER ((MDIV_405 << 12) | (PDIV_405 << 4) | (SDIV_405))
/* initialize system clocks */
ldr r0, =LOCKTIME
ldr r1, =0xffffff
str r1, [r0]
/* FCLK:HCLK:PCLK */
ldr r0, =CAMDIVN
mov r1, #0
str r1, [r0]
ldr r0, =CLKDIVN
ldr r1, =CLKDIVN_VAL
str r1, [r0]
mrc p15, 0, r1, c1, c0, 0 @ read ctrl register
orr r1, r1, #0xc0000000 @ Asynchronous
mcr p15, 0, r1, c1, c0, 0 @ write ctrl register
/* UPLL setup */
ldr r0, =UPLLCON
ldr r1, upll_value_USER /*???????*/
str r1, [r0]
nop
nop
nop
nop
nop /* wait until upll has the effect */
nop
nop
nop
/* PLL setup */
ldr r0, =MPLLCON
ldr r1, mpll_value_USER/*???????*/
str r1, [r0]
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit /*cpu init*/
#endif
/*#ifdef CONFIG_S3C2440_NAND_BOOT*/
/* reset NAND */
mov r1, #NAND_CTL_BASE
ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )
str r2, [r1, #oNFCONF]
ldr r2, [r1, #oNFCONF]
ldr r2, =( (1<<4)|(0<<1)|(1<<0) ) /* Active low CE Control */
str r2, [r1, #oNFCONT]
ldr r2, [r1, #oNFCONT]
ldr r2, =(0x6) /* RnB Clear */
str r2, [r1, #oNFSTAT]
ldr r2, [r1, #oNFSTAT]
mov r2, #0xff /* RESET command */
strb r2, [r1, #oNFCMD]
mov r3, #0 /* wait */
nand1:
add r3, r3, #0x1
cmp r3, #0xa
blt nand1
nand2:
ldr r2, [r1, #oNFSTAT] /* wait ready */
tst r2, #0x4
beq nand2
ldr r2, [r1, #oNFCONT]
orr r2, r2, #0x2 /* Flash Memory Chip Disable */
str r2, [r1, #oNFCONT]
/* get read to call C functions (for nand_read()) */
ldr sp, DW_STACK_START /* setup stack pointer */
mov fp, #0 /* no previous frame, so fp="0" */
/* copy U-Boot to RAM */
ldr r0, =_TEXT_BASE
mov r1, #0x0
mov r2, #0x20000
bl nand_read_ll/*????? LCALL C FILE*/
tst r0, #0x0
beq ok_nand_read
bad_nand_read:
loop2: b loop2 /* infinite loop */
ok_nand_read:
/* verify */
mov r0, #0
ldr r1, =_TEXT_BASE
mov r2, #0x400 /* 4 bytes * 1024 = 4K-bytes */
go_next:
ldr r3, [r0], #4
ldr r4, [r1], #4
teq r3, r4
bne notmatch
subs r2, r2, #4
beq stack_setup
bne go_next
notmatch:
loop3: b loop3 /* infinite loop */
/*#endif */
/* CONFIG_S3C2440_NAND_BOOT*/
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
/**LED**/
LDR R0,=0x56000010
MOV R1,#0x15400 /*rGPBCON = 0x15400*/
STR R1,[R0]
LDR R0,=0x56000014 /*rGPBDAT |= LED_MSK*/
MOV R1,#0x1E0
STR R1,[R0]
LDR R0,=0x56000014 /*rGPBDAT &= LED1*/
MOV R1,#0xBF /*rGPBDAT &= LED4*/
STR R1,[R0]
/**LED**/
ldr pc, _start_armboot
_start_armboot: .word start_armboot
/*zou add*/
.align 2
DW_STACK_START: .word STACK_BASE+STACK_SIZE-4
.align 4
mpll_value_USER:
.long vMPLLCON_NOW_USER
upll_value_USER:
.long vUPLLCON_NOW_USER
/*zou add*/ |
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