原代码如下：
library ieee;
use ieee.std_logic_1164.all;
----------------------------
entity ands is
port(a,aa: in std_logic;
b,bb: in std_logic;
c:out std_logic
);
end entity;
--************************--
architecture one of ands is
begin
process(a,b,aa,bb)
begin
if((aa='1')or(bb='1'and bb'event))then
c<=a or b;
end if;
end process;
end architecture;
--******************
----*****************
出错信息如下：
Error (10626): VHDL error at ands.vhd(17): can't implement clock enable condition specified using binary operator "or"
Error (10658): VHDL Operator error at ands.vhd(17): failed to evaluate call to operator ""or""
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Elaboration was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 170 megabytes
Error: Processing ended: Tue Sep 29 10:02:32 2009
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:01 |
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