奇美7寸 TFT接口如下：
Pin Name I/O Description
1 GND I Power Ground
2 VGL I Gate OFF Power Supply Voltage
3 VGL I Gate OFF Power Supply Voltage
4 /XAO I Output all-on control
When /XAO is set to L, all outputs are fixed to VGH
5 VDDG I Gate Driver Power supply (+3.3V)
6 VDDG I Gate Driver Power supply (+3.3V)
7 GND I Power Ground
8 VGH I Gate ON Power Supply Voltage
9 UD I
Gate Driver Up/down scan setting
When UD=H, reverse scan
When UD=L, normal scan (Default pull low)
10 DE I Input data enable control
When DE mode, active High to enable data input. (Default pull low)
11 FRC I
Dithering control setting
When FRC=H, the width of data input 8 bits
When FRC=L, the width of data input 6 bits and set Dx0 and Dx1 to logical low
(Default pull low)
12 B07 I Blue data (MSB)
13 B06 I Blue data
14 B05 I Blue data
15 B04 I Blue data
16 B03 I Blue data
17 B02 I Blue data
18 B01 I Blue data
19 B00 I Blue data (LSB)
20 CLK I Clock signal
User can input different polarity CLK by EDGSL setting. (Default pull low)
21 GND I Power Ground
22 G07 I Green data (MSB)
23 G06 I Green data
24 G05 I Green data
25 G04 I Green data
26 G03 I Green data
27 G02 I Green data
28 G01 I Green data
29 G00 I Green data (LSB)
30 R07 I Red data (MSB)
31 R06 I Red data
32 R05 I Red data
33 R04 I Red data
34 R03 I Red data
36 R01 I Red data
37 R00 I Red data (LSB)
38 RESETB I Hardware global reset. Low active (Default pull high)
39 EDGSL I
Define input clock polarity
When EDGSL=L, Latch data by rising edge of CLK (Default Pull Low)
When EDGSL=H, CLK polarity is inverted, Latch data by falling edge of CLK
40 LR I
Shift direction of Source Driver IC internal shift register is controlled by this pin as
show below:
LR=H SO1 |
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