http://infocenter.arm.com/help/t ... tex_m3_r2p0_trm.pdf
1.7.3. Differences in functionality between r1p1 and r2p0
In summary, the differences in functionality include:
1, Implementation time options have been added to select between different levels of debug and trace support. This has replaced the previous TIEOFF_FPBEN and TIEOFF_TRCENA options.
2, New implementation option to enable the resetting of all registers within the processor.
3, Architectural clock gating inclusion is now controlled using one implementation option.
4, DBGRESTART input and DBGRESTARTED output has been added for use in debugging multi-core systems. See the ARMv7-M Architecture Reference Manual for more information.
5, SLEEPHOLDREQn input and SLEEPHOLDACKn have been added to enable the extension of SLEEPING. See Extending sleep.
6, The APB interface has been upgraded from v2.0 to v3.0. See External private peripheral interface.
7, A new output signal called INTERNALSTATE has been added that enables observation of some of the internal state of the core if the OBSERVATION implementation option is used.
8, An Auxiliary Control Register has been added with new functionality disable bits to:
stop interruption of load/store multiples, divides and multiplies
stop IT folding
disable the write buffers in Cortex-M3 for default memory map accesses.
For details on the Auxiliary Control Register see Auxiliary Control Register.
9, The STKALIGN bit reset value in the Configuration and Control Register at address 0xE000ED14 has been inverted. The reset value is now 1, which means that the stack frame is 8-byte aligned by default. Configuration Control Register.
10, Addition of a Wake-up Interrupt Controller to minimize logic in always clocked domain during sleep. For details see Using the Wake-up Interrupt Controller.
11, Addition of FIXHMASTERTYPE pin to prevent debugger marking AHB transactions as core data side if required.
12, Errata fixes to the r1p1 release.
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