首先是滤波，然后是技术，最后是选择输出，应该是比较简单的，怎么就出不来啊
------------------主程序-----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-------------------------------------------
entity guangshan is
port(
clk_8M: in std_logic; --CPLD系统时钟输入
--clk_4M: inout std_logic;--分频出4M
--clk_1M: inout std_logic;--分频出4M
c1a: in std_logic; --长度计1A相输入
c1b: in std_logic; --长度计1B相输入
c1z: in std_logic; --长度计1Z相输入
c2a: in std_logic; --长度计2A相输入
c2b: in std_logic; --长度计2B相输入
c2z: in std_logic; --长度计2Z相输入
g1a: in std_logic; --光栅尺A相输入
g1b: in std_logic; --光栅尺B相输入
g1z: in std_logic; --光栅尺Z相输入
countout: out std_logic_vector(15 downto 0); --计数值输出
--countin: in std_logic_vector(15 downto 0);
xrw: in std_logic; --读写选择
we: in std_logic; --写使能
oe: in std_logic; --读使能
ce: in std_logic; --片选信号
rest: in std_logic; --复位信号
CH: in std_logic_vector(1 downto 0)
); --数据选择信号
end guangshan;
architecture behave of guangshan is
SIGNAL c1count : std_logic_vector(15 downto 0); --长度计1的计数值
signal c2count : std_logic_vector(15 downto 0); --长度计2的计数值
signal g1count : std_logic_vector(23 downto 0); --光栅尺1的计数值
signal c1eca_now,c1ecb_now : std_logic; --长度计1的AB相电平
signal c2eca_now,c2ecb_now : std_logic; --长度计2的AB相电平
signal g1eca_now,g1ecb_now : std_logic; --光栅尺1的AB相电平
signal c1filtal : std_logic_vector(1 downto 0);
signal c1filtah : std_logic_vector(1 downto 0); --长度计1的A相滤波次数
signal clfiltbl,c1filtbh : std_logic_vector(1 downto 0); --长度计1的B相滤波次数
signal c2filtal,c2filtah : std_logic_vector(1 downto 0); --长度计2的A相滤波次数
signal c2filtbl,c2filtbh : std_logic_vector(1 downto 0); --长度计2的B相滤波次数
signal glfiltal,g1filtah : std_logic_vector(1 downto 0); --光栅尺1的A相滤波次数
signal glfiltbl,g1filtbh : std_logic_vector(1 downto 0); --光栅尺1的B相滤波次数
begin
----------------------------------------------------------------------------------------------
process(clk_8M,c1a,rest,c1filtah,c1filtal) --长度计1的A相电平确定
begin
if(rest='0')then
c1eca_now<='0';
c1filtal<="00";
c1filtah<="00";
elsif(clk_8M'event and clk_8M='1')then
if(c1a='1')then
c1filtal<="00";
if(c1filtah="10")then
c1eca_now<='1';
c1filtah<="00";
else
c1filtah<=c1filtah+'1';
end if;
else
c1filtah<="00";
if(c1filtal="10")then
c1eca_now<='0';
c1filtal<="00";
else
c1filtal<=c1filtal+'1';
end if;
end if;
end if;
end process;
----------------------------------------------------------
process(clk_8M,rest) --长度计1的B相电平确定
begin
if(rest='0')then
c1ecb_now<='0';
clfiltbl<="00";
c1filtbh<="00";
elsif(clk_8M'event and clk_8M='1')then
if(c1b='1')then
clfiltbl<="00";
if(c1filtbh="10")then
c1ecb_now<='1';
else
c1filtbh<=c1filtbh+1;
end if;
else
c1filtbh<="00";
if(clfiltbl="10")then
c1ecb_now<='0';
else
clfiltbl<=clfiltbl+1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
process(rest,c1eca_now,c1ecb_now) --长度计1计数值运算
variable c1state : std_logic_vector (3 DOWNTO 0);
begin
if(rest='0')then
c1state:="0000";
c1count<="0000000000000000";
else
c1state(3) :=c1state(1);
c1state(1) :=c1eca_now;
c1state(2) :=c1state(0);
c1state(0) :=c1ecb_now;
if(c1state="1011")then
c1count<=c1count+1;
elsif(c1state="1110")then
c1count<=c1count-1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
process(clk_8M,ce,oe,CH) --数据输出
begin
if(ce='0' and oe='0')then
case CH is
when "00" => countout<=c1count;
--when "01" => countout<=c2count;
--when "10" => countout<=g1count(15 downto 0);
--when "11" => countout(7 downto 0)<=g1count(23 downto 16);
when others=>countout<="0000000000000000";
end case;
end if;
end process;
----------------------------------------------------------------------------------------
end behave; |
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