library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
entity dingshiqi is
TYPE time is range -1E8 to 1E8;
UNITS nasecs;
secs=1000000000 nasecs;
END UNITS;
Port ( clk : in std_logic;
Curptptime_secs:out time;
Curptptime_nasecs: out time);
--divclk : out std_logic);
end dingshiqi;
architecture Behavioral of dingshiqi is
signal counter0 : std_logic_vector(4 downto 0):="00000";
signal counter1 : std_logic_vector(7 downto 0):="11111111";
signal tempdivclk: std_logic:='0';
signal tempcurptptime_secs:time;
signal tempcurptptime_nasecs:time;
signal cv:std_logic_vector(4 downto 0):="00000";
begin
process(clk) --Divclk
begin
if clk'event and clk='1' then
if(counter0>="11111") then
counter0<="00000";
tempdivclk<=not tempdivclk;
else
counter0<=counter0+'1';
end if;
end if;
end process;
process(tempdivclk) --counter
begin
if tempdivclk'event and tempdivclk='1' then
if(counter1<="00000000") then
counter1<="11111111";
else
counter1<=counter1-'1';
cv<=counter1;
end if;
end if;
tempcurptptime_nasecs<=cv*64000+16384000;
end process;
Curptptime_nasecs<=tempcurptptime;
if Curptptime_nasecs>1000000000-1 then
Curptptime_nasecs<=Curptptime_nasecs-1000000000;
Curptptime_secs<=Curptptime_secs+1;
end if;
end Behavioral;
大家帮我看看，那里有问题啊，一直编译不通过。
编译出错是** Error: D:/ModelSim/examples/dingshiqi.vhd(7): near "TYPE": expecting: END |
楼主
标题置顶
标题高亮
