特性
High-Performance Automotive-Grade Microcontroller for Safety-Critical ApplicationsDual CPUs Running in Lockstep
ECC on Flash and RAM Interfaces
Built-In Self-Test (BIST) for CPU and On-chip RAMs
Error Signaling Module With Error Pin
Voltage and Clock Monitoring
ARM Cortex-R4F 32-Bit RISC CPU 1.66 DMIPS/MHz With 8-Stage Pipeline
FPU With Single- and Double-Precision
12-Region Memory Protection Unit (MPU)
Open Architecture With Third-Party Support
Operating ConditionsUp to 180-MHz System Clock
Core Supply Voltage (VCC): 1.14 to 1.32 V
I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
Integrated Memory1.25MB of Program Flash With ECC
192KB of RAM With ECC
64KB of Flash for Emulated EEPROM With ECC
16-Bit External Memory Interface (EMIF)
Common Platform ArchitectureConsistent Memory Map Across Family
Real-Time Interrupt (RTI) Timer (OS Timer)
128-Channel Vectored Interrupt Module (VIM)
2-Channel Cyclic Redundancy Checker (CRC)
Direct Memory Access (DMA) Controller16 Channels and 32 Control Packets
Parity Protection for Control Packet RAM
DMA Accesses Protected by Dedicated MPU
Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
Separate Nonmodulating PLL
IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
Advanced JTAG Security Module (AJSM)
Calibration CapabilitiesParameter Overlay Module (POM)
16 General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts
Enhanced Timing Peripherals for Motor Control7 Enhanced Pulse Width Modulator (ePWM) Modules
6 Enhanced Capture (eCAP) Modules
2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
Two Next Generation High-End Timer (N2HET) ModulesN2HET1: 32 Programmable Channels
N2HET2: 18 Programmable Channels
160-Word Instruction RAM Each With Parity Protection
Each N2HET Includes Hardware Angle Generator
Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
Two 12-Bit Multibuffered Analog-to-Digital Converter (MibADC) ModulesADC1: 24 Channels
ADC2: 16 Channels Shared With ADC1
64 Result Buffers Each With Parity Protection
Multiple Communication InterfacesThree CAN Controllers (DCANs)64 Mailboxes Each With Parity Protection
Compliant to CAN Protocol Version 2.0A and 2.0B
Inter-Integrated Circuit (I2C)
Three Multibuffered Serial Peripheral Interface (MibSPI) Modules128 Words Each With Parity Protection
8 Transfer Groups
Up to Two Standard Serial Peripheral Interface (SPI) Modules
Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support
Packages144-Pin Quad Flatpack (PGE) [Green]
337-Ball Grid Array (ZWT) [Green]
All trademarks are the property of their respective owners.
|
楼主
