.a51程序中关于高速状态下端点的设置：
HighSpeedConfigDscr:
db DSCR_CONFIG_LEN ;; Descriptor length
db DSCR_CONFIG ;; Descriptor type
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB)
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB)
db 1 ;; Number of interfaces
db 1 ;; Configuration number
db 0 ;; Configuration string
db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) , set the power model
db 50 ;; Power requirement (div 2 ma),100mA
;; Interface 0 Descriptor
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 0 ;; interface descriptor Alt. setting 0, modified by wangqf at 20100312-14:54
db 2 ;; Number of end points, modifid by wangqf at 20100311
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index
;; Endpoint2 Descriptor; ISO, IN, 1*1024/uFrame
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint number, and direction :EP2,and IN
db ET_ISO ;; Endpoint type :
db 00H ;; Maximun packet size (LSB) :bit12:11 decide the xKBytes, 00-->none; 01-->1 additional; 10-->2additional
db 04H ;; Max packect size (MSB) :EP2 is double buffer, each is 1KBytes;
db 01H ;; Polling interval
;; Endpoint6 Descriptor: ISO, OUT, 1*1024/uFrame
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 06H ;; Endpoint number, and direction: EP6, and OUT
db ET_ISO ;; Endpoint type
db 00H ;; Maximun packet size (LSB) :bit12:11 decide the xKBytes, 00-->none; 01-->1 additional; 10-->2additional
db 04H ;; Max packect size (MSB):EP6 is double buffer, each is 1KBytes
db 01H ;; Polling interval
HighSpeedConfigDscrEnd:
TD_int()程序为：
void TD_Init(void) // Called once at startup
{
/*--------------------------------------------------------------------
CPU Control and Status
CPUCS: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 0
PORTCSTB: 1-->match PORTC and RD, WR; 0-->when 128 Pin, should set 0;
CLKSPD1:0:00-->12MHz; 01-->24MHz; 10-->48MHz; 11-->Reserved
CLKINV: 0-->CLKOUT signal not inverted; 1-->CLKOUT signal inverted
CLKOE: 0-->CLKOUT pin driven; 1-->CLKOUT signal pin floats;
--------------------------------------------------------------------*/
CPUCS =0x16; //48MHz, inverted, clkout;
SYNCDELAY;
/*---------------------------------------------------------------------
REVCTL.1-->DYN_OUT
REVCTL.0-->ENH_PKT
---------------------------------------------------------------------*/
REVCTL |= 0x03;
SYNCDELAY;
/*----------------------------------------------------------------------------
Interface Configuration
IFCONFIG: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
IFCLKSRC 3048MHz IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0
IFCLKSRC: 0-->IFCLK use external clock; 1-->IFCLK use interanl 30 ro 48MHz clock
3048MHZ: 0-->30MHz; 1-->48MHz
IFCLKOE: 0-->Tri-state; 1-->Drive
IFCLKPOL: 0-->clock is not inverted; 1-->clock is inverted
ASYNC: 0-->FIFO/GPIF operates syn; 1-->FIFO/GPIF operates asyn
GSTATE: 0-->I/O portE; 1-->portE[2:0] is special functional
IFCFG1:0: 00-->Ports; 01-->Reserved; 10-->GPIF interface(internal master); 11-->Slave FIFO interface(external master)
-----------------------------------------------------------------------------*/
IFCONFIG = 0x43; //internal clock, 48MHz, Drive, inverted, synchronous, Slave FIFO interface
SYNCDELAY;
/*--------------------------------------------------------------------
EPXCFG: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
valid dir type1 type0 size 0 buffer1 buffer0
valid: active or not
dir : 0 out; 1 IN
type[1..0]:
00-->invalid
01-->isochronous
10-->bulk
11-->interrupt
size : 0-->512 Bytes; 1-->1024Bytes; //only for endpoint2 and endpoint6
buffer[1..0]:
00-->quad
01-->invaid
10-->double
11-->triple
--------------------------------------------------------------------*/
// Using endpoints 2 & 6, zero the valid bit on all others
EP2CFG = 0xDA; // EP2: DIR=IN, TYPE=ISOC, SIZE=1024, BUF=2x
SYNCDELAY;
EP6CFG = 0x9A; // EP6: DIR=OUT, TYPE=ISOC, SIZE=1024, BUF=2x
SYNCDELAY;
EP1OUTCFG = (EP1OUTCFG & 0x7F);
SYNCDELAY;
EP1INCFG = (EP1INCFG & 0x7F);
SYNCDELAY;
EP4CFG = (EP4CFG & 0x7F);
SYNCDELAY;
SYNCDELAY;
EP8CFG = (EP8CFG & 0x7F);
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
/*---------------------------------------------------------------------
The following process is used to set the EPXFIFOCFG
EPxFIFOCFG: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE
WORDWIDE data bus width:0-->8bits; 1-->16bits;
ZEROLENIN can whether send a zero length frame or not
OEP1 empty flag early one clock befor realily
INFM1 full flag early one clock befor realily;
---------------------------------------------------------------------*/
EP2FIFOCFG &=0x0C; //EP2:AUTOIN, ZEROLENIN, 8Bits, INFM1
SYNCDELAY;
EP2FIFOCFG &=0x0C; //EP2:AUTOIN, ZEROLENIN, 8Bits, INFM1
SYNCDELAY;
EP6FIFOCFG &=0x30; //EP6:AUTOOUT, OEP1, 8Bits
SYNCDELAY;
EP6FIFOCFG &=0x30; //EP6:AUTOOUT, OEP1, 8Bits
SYNCDELAY;
//EP4FIFOCFG &=0x60; //EP4 8bits
//SYNCDELAY;
//EP8FIFOCFG &=0x60; //EP8 8bits
//SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x01;
//Set the autoin length is 640
//*----------------------------
SYNCDELAY;
EP2AUTOINLENH =0x03;//0x02;
SYNCDELAY;
EP2AUTOINLENH =0x03;//0x02;
SYNCDELAY;
EP2AUTOINLENL =0xFF;//0x80;
SYNCDELAY;
EP2AUTOINLENL =0xFF;//0x80;
SYNCDELAY;
//----------------------------*/
// OUT endpoints do NOT come up armed
EP6BCL = 0x80; // arm first buffer by writing BC w/skip=1
SYNCDELAY;
EP6BCL = 0x80; // arm second buffer by writing BC w/skip=1
SYNCDELAY;
//AUTOPTRSETUP |= 0x01; // enable dual autopointer feature
Rwuen = TRUE;
}
TD_POLL()程序为：
void TD_Poll(void) // Called repeatedly while the device is idle
{
// check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP6EMPTY))
{
EP6BCL = 0x80; // re(arm) EP6OUT
SYNCDELAY;
EP6BCL =0x80;
SYNCDELAY;
}
}
程序的框架是从开发板厂商那边获得的关于块传输的例程修改的，我只修改了.a51、TD_INT和TD_POLL两个函数，其它的框架没有修改。
具体的配置：
EP2: ISO, 1024B，double， AUTOIN, AUTOINLEN=1023, 支持0字节传输，8位数据总线
EP6：ISO, 1024B, double, AUTOOUT,
系统时钟：48MHz
IFCLK:外部24MHz
现在的问题是我在用CY官方给的调试助手上无法接受到同步传输的数据，只能写不能读，还请各位高手不吝指教！
谢谢！ |
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