大神,求教下16位的和8位的怎么通讯,
16位的编程
/*
* File: newmain.c
* Author: hjy
*
* Created on 2016?8?16?, ??3:22
*/
// FICD
#pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
// FPOR
#pragma config ALTI2C1 = OFF // Alternate I2C1 pins (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF // Alternate I2C2 pins (I2C2 mapped to SDA2/SCL2 pins)
#pragma config WDTWIN = WIN25 // Watchdog Window Select bits (WDT Window is 25% of WDT period)
// FWDT
#pragma config WDTPOST = PS32768 // Watchdog Timer Postscaler bits (1:32,768)
#pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
#pragma config PLLKEN = ON // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
// FOSC
#pragma config POSCMD = XT // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = ON // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
#pragma config IOL1WAY = OFF // Peripheral pin select configuration (Allow only one reconfiguration)
#pragma config FCKSM = CSDCMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
// FOSCSEL
#pragma config FNOSC = PRIPLL // Oscillator Source Selection (Internal Fast RC (FRC))
#pragma config PWMLOCK = ON // PWM Lock Enable bit (Certain PWM registers may only be written after key sequence)
#pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)
// FGS
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GCP = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include <xc.h>
#include "p33EP64MC202.h"
void init_U1RX(void);
int Rflag;
char ReceivedChar;
int main()
{
CLKDIVbits.PLLPRE=0; //N1=2,4MHz
PLLFBDbits.PLLDIV=38; //M=40,160MHz
CLKDIVbits.PLLPOST=1; //N2=4,40MHz
//Fcy=20MHz Tcy=50ns
while(OSCCONbits.COSC!=0b011); //??????
OSCCONbits.IOLOCK=0;
OSCCONbits.COSC0=0;
OSCCONbits.COSC1=1;
OSCCONbits.COSC2=1;
ANSELB=0x0000;
ANSELA=0x0000;
TRISBbits.TRISB4=0;
TRISAbits.TRISA4=1;
RPOR1=0x0001;
RPINR18=0x0014;
init_U1RX() ;
while(1)
{
if(ReceivedChar==0xaa)
{
TRISB=0x0000;
PORTB=0x0000;
}
}
}
void init_U1RX()
{
U1MODEbits.UARTEN =0;
IFS0bits.U1TXIF=0;
IPC3bits.U1TXIP=1;
IEC0bits.U1TXIE = 0;
IFS0bits.U1RXIF=0;
IPC2bits.U1RXIP=1;
IEC0bits.U1RXIE= 1;
U1BRG = 129; // Baud Rate setting for 9600
U1MODEbits.STSEL = 0; // 1-stop bit
U1MODEbits.PDSEL0 = 0;// No Parity, 8-data bits
U1MODEbits.PDSEL1 = 0;
U1MODEbits.ABAUD = 0; // Auto-Baud disabled
U1MODEbits.BRGH = 0;
U1MODEbits.UEN0=0;
U1MODEbits.UEN1=0;
U1STAbits.URXISEL0=0;
U1STAbits.URXISEL1=0;
U1MODEbits.UARTEN=1;
U1STAbits.UTXEN=1;
}
void __attribute__((__interrupt__,no_auto_psv)) _U1RXInterrupt(void)
{
if(U1STAbits.OERR == 1)
{
U1STAbits.OERR = 0;
}
if(U1STAbits.URXDA==1)
{
IFS0bits.U1RXIF=0;
ReceivedChar=U1RXREG;
}
}
8位的编程
/*/*
* File: main.c
* Author: Administrator
*
* Created on 2016?9?13?, ??9:07
*/
// PIC18F25K80 Configuration Bit Settings
// 'C' source line config statements
// CONFIG1L
#pragma config RETEN = OFF // VREG Sleep Enable bit (Ultra low-power regulator is Disabled (Controlled by REGSLP bit))
#pragma config INTOSCSEL = HIGH // LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep)
#pragma config SOSCSEL = DIG // SOSC Power Selection and mode Configuration bits (Digital (SCLKI) mode)
#pragma config XINST = OFF // Extended Instruction Set (Disabled)
// CONFIG1H
#pragma config FOSC = HS1 // Oscillator (XT oscillator)
#pragma config PLLCFG = OFF // PLL x4 Enable bit (Disabled)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor (Disabled)
#pragma config IESO = OFF // Internal External Oscillator Switch Over Mode (Disabled)
// CONFIG2L
#pragma config PWRTEN = OFF // Power Up Timer (Disabled)
#pragma config BOREN = OFF // Brown Out Detect (Disabled in hardware, SBOREN disabled)
#pragma config BORV = 2 // Brown-out Reset Voltage bits (2.0V)
#pragma config BORPWR = ZPBORMV // BORMV Power level (ZPBORMV instead of BORMV is selected)
// CONFIG2H
#pragma config WDTEN = OFF // Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
#pragma config WDTPS = 256 // Watchdog Postscaler (1:256)
// CONFIG3H
#pragma config CANMX = PORTB // ECAN Mux bit (ECAN TX and RX pins are located on RB2 and RB3, respectively)
#pragma config MSSPMSK = MSK7 // MSSP address masking (7 Bit address masking mode)
#pragma config MCLRE = ON // Master Clear Enable (MCLR Enabled, RE3 Disabled)
// CONFIG4L
#pragma config STVREN = ON // Stack Overflow Reset (Enabled)
#pragma config BBSIZ = BB2K // Boot Block Size (2K word Boot Block size)
// CONFIG5L
#pragma config CP0 = OFF // Code Protect 00800-01FFF (Disabled)
#pragma config CP1 = OFF // Code Protect 02000-03FFF (Disabled)
#pragma config CP2 = OFF // Code Protect 04000-05FFF (Disabled)
#pragma config CP3 = OFF // Code Protect 06000-07FFF (Disabled)
// CONFIG5H
#pragma config CPB = OFF // Code Protect Boot (Disabled)
#pragma config CPD = OFF // Data EE Read Protect (Disabled)
// CONFIG6L
#pragma config WRT0 = OFF // Table Write Protect 00800-01FFF (Disabled)
#pragma config WRT1 = OFF // Table Write Protect 02000-03FFF (Disabled)
#pragma config WRT2 = OFF // Table Write Protect 04000-05FFF (Disabled)
#pragma config WRT3 = OFF // Table Write Protect 06000-07FFF (Disabled)
// CONFIG6H
#pragma config WRTC = OFF // Config. Write Protect (Disabled)
#pragma config WRTB = OFF // Table Write Protect Boot (Disabled)
#pragma config WRTD = OFF // Data EE Write Protect (Disabled)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protect 00800-01FFF (Disabled)
#pragma config EBTR1 = OFF // Table Read Protect 02000-03FFF (Disabled)
#pragma config EBTR2 = OFF // Table Read Protect 04000-05FFF (Disabled)
#pragma config EBTR3 = OFF // Table Read Protect 06000-07FFF (Disabled)
// CONFIG7H
#pragma config EBTRB = OFF // Table Read Protect Boot (Disabled)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include "pic18f25k80.h"
void initCOM(void);
void main()
{
OSCCONbits.SCS0=0;
OSCCONbits.SCS1=0;
initCOM();
INTCONbits.GIE=1; //??????
INTCONbits.PEIE=1;
IPR1bits.TX1IP=1;//??????
PIE1bits.TX1IE=0;
while(1)
{
TXREG1=0xaa;
}
}
void initCOM()
{
TRISCbits.TRISC6=0;
TRISCbits.TRISC7=1;
TXSTA1=0x20;
RCSTA1=0x90;
SPBRG=51; //SYNC=0;BRGH=0;BRG16=1; ??? 8MHZ??
BAUDCON1=0x08;
} |