#define CCxxx0_PARTNUM 0x30
#define CCxxx0_VERSION 0x31
#define CCxxx0_FREQEST 0x32
#define CCxxx0_LQI 0x33
#define CCxxx0_RSSI 0x34
#define CCxxx0_MARCSTATE 0x35
#define CCxxx0_WORTIME1 0x36
#define CCxxx0_WORTIME0 0x37
#define CCxxx0_PKTSTATUS 0x38
#define CCxxx0_VCO_VC_DAC 0x39
#define CCxxx0_TXBYTES 0x3A
#define CCxxx0_RXBYTES 0x3B
#define CCxxx0_PATABLE 0x3E
#define CCxxx0_TXFIFO 0x3F
#define CCxxx0_RXFIFO 0x3F
// RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
typedef struct S_RF_SETTINGS
{
INT8U FSCTRL2; //自已加的
INT8U FSCTRL1; // Frequency synthesizer control.
INT8U FSCTRL0; // Frequency synthesizer control.
INT8U FREQ2; // Frequency control word, high INT8U.
INT8U FREQ1; // Frequency control word, middle INT8U.
INT8U FREQ0; // Frequency control word, low INT8U.
INT8U MDMCFG4; // Modem configuration.
INT8U MDMCFG3; // Modem configuration.
INT8U MDMCFG2; // Modem configuration.
INT8U MDMCFG1; // Modem configuration.
INT8U MDMCFG0; // Modem configuration.
INT8U CHANNR; // Channel number.
INT8U DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
INT8U FREND1; // Front end RX configuration.
INT8U FREND0; // Front end RX configuration.
INT8U MCSM0; // Main Radio Control State Machine configuration.
INT8U FOCCFG; // Frequency Offset Compensation Configuration.
INT8U BSCFG; // Bit synchronization Configuration.
INT8U AGCCTRL2; // AGC control.
INT8U AGCCTRL1; // AGC control.
INT8U AGCCTRL0; // AGC control.
INT8U FSCAL3; // Frequency synthesizer calibration.
INT8U FSCAL2; // Frequency synthesizer calibration.
INT8U FSCAL1; // Frequency synthesizer calibration.
INT8U FSCAL0; // Frequency synthesizer calibration.
INT8U FSTEST; // Frequency synthesizer calibration control
INT8U TEST2; // Various test settings.
INT8U TEST1; // Various test settings.
INT8U TEST0; // Various test settings.
INT8U IOCFG2; // GDO2 output pin configuration
INT8U IOCFG0; // GDO0 output pin configuration
INT8U PKTCTRL1; // Packet automation control.
INT8U PKTCTRL0; // Packet automation control.
INT8U ADDR; // Device address.
INT8U PKTLEN; // Packet length.
} RF_SETTINGS;
/////////////////////////////////////////////////////////////////
const RF_SETTINGS rfSettings =
{
0x00,
0x08, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x10, // FREQ2 Frequency control word, high byte.
0xA7, // FREQ1 Frequency control word, middle byte.
0x62, // FREQ0 Frequency control word, low byte.
0x5B, // MDMCFG4 Modem configuration.
//0xf6, // MDMCFG4 chang by allen
0xF8, // MDMCFG3 Modem configuration.
//0x83, // MDMCFG3 chang by allen data rate = 2.398K
0x03, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x47, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x11, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x0B, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
//0x05, // PKTCTRL0 Packet automation control.
0x01, //PKTCTRL0 crc disable chang by allen at 09.12.24
0x00, // ADDR Device address.
0x0c // PKTLEN Packet length.
};