- #include <csl.h>
- #include <csl_i2c.h>
- #include <stdio.h>
- #include <csl_pll.h>
- #include <csl_mcbsp.h>
- #include <csl_dma.h>
- #include <csl_irq.h>
- //---------Global constants---------
- #define N 128
- #define CODEC_ADDR 0x1A //AIC23在I2C总线上的从地址0011010
- #pragma DATA_SECTION(aic23data,"dmaMem")
- int aic23data ;
- int pingrcv[N], pongrcv[N], pingxmt[N], pongxmt[N],Leftchannel_Buffer[N],Rightchannel_Buffer[N];
- int xfreebuf,rfreebuf,xpongbuf,rpongbuf,xpingbuf,rpingbuf;
- int xmtEventId,rcvEventId;
- Uint16 i,temp;
- Uint16 i2c_status;
- I2C_Config testI2C;
- MCBSP_Handle hMcbsp;
- DMA_Handle hDmaRcv, hDmaXmt;
- int RecvComplete;
- Uint16 dmaXmtIsr_count=0; //计数进入传送中断的次数
- Uint16 dmaRcvIsr_count=0; //计数进入接收中断的次数
- Uint16 sin=0; //计数进入signal函数的次数
- interrupt void dmaXmtIsr(void);
- interrupt void dmaRcvIsr(void);
- extern void VECSTART(void);
- /*锁相环的设置*/
- PLL_Config myConfig = {
- 0, //IAI: the PLL locks using the same process that was underway
- //before the idle mode was entered
- 1, //IOB: If the PLL indicates a break in the phase lock,
- //it switches to its bypass mode and restarts the PLL phase-locking
- //sequence
- 24, //PLL multiply value; multiply 24 times
- 1 //Divide by 2 PLL divide value; it can be either PLL divide value
- //(when PLL is enabled), or Bypass-mode divide value
- //(PLL in bypass mode, if PLL multiply value is set to 1)
- };
- /*******************************************************************************************/
- /**********************************MCBSP设置************************************************/
- MCBSP_Config Mcbsptest;
- /*McBSP set,we use mcbsp1 to send and recieve the data between DSP and AIC23*/
- MCBSP_Config Mcbsp1Config= {
- MCBSP_SPCR1_RMK(
- // MCBSP_SPCR1_DLB_OFF, /* DLB = 0,禁止自闭环方式 */
- MCBSP_SPCR1_DLB_ON, /* DLB = 1 */
- //MCBSP_SPCR1_RJUST_LZF, /* RJUST = 2 left justify the data and zero fill LSBS */
- MCBSP_SPCR1_RJUST_RZF, /* RJUST = 0 */
- MCBSP_SPCR1_CLKSTP_DISABLE, /* CLKSTP = 0 Clock stop mode disable */
- //MCBSP_SPCR1_DXENA_ON, /* DXENA = 1 DX delay enabler on */
- MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
- MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 reserved always write 0*/
- MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 sends a receive INT request to CPU when the RRDY bit
- change from 0 to 1, indicating that receive data is ready to be read*/
- 0, /* RSYNCER = 0 receive frame-sync error bit, no error*/
- MCBSP_SPCR1_RRST_DISABLE /* RRST = 0 reset the receiver*/
- ),
- MCBSP_SPCR2_RMK(
- MCBSP_SPCR2_FREE_NO, /* FREE = 0 free run bit, The McBSP transmit and receive clocks are affected as determined by the SOFT bit*/
- MCBSP_SPCR2_SOFT_NO, /* SOFT = 0 Soft stop bit, Hard stop*/
- MCBSP_SPCR2_FRST_FSG, /* FRST = 0 Frame-sync logic reset bit*/
- MCBSP_SPCR2_GRST_CLKG, /* GRST = 0 Sample rate generator reset bit */
- MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 transmit interrupt mode bits XRDY bit changes from 0 to1 */
- 0, /* XSYNCERR = N/A transmit frame-sync error bit, no error*/
- MCBSP_SPCR2_XRST_DISABLE /* XRST = 0 transmit ready bit, not ready*/
- //注意：开始一定要设置为disable，否则不能设置它的寄存器，全部为默认值，导致不能正常接收，
- //在程序调用C库函数mcbspstart时会在设为1，McBSP便退出reset状态开始工作
- ),
- /*单数据相，接受数据长度为16位,每相2个数据*/
- MCBSP_RCR1_RMK(
- //MCBSP_RCR1_RFRLEN1_OF(1), /* RFRLEN1 = 1 Receive frame length 1 bits(1 to 128 words),Frame length=(RFRLEN1+1)words*/
- MCBSP_RCR1_RFRLEN1_OF(0), /* RFRLEN1 = 0 */
- MCBSP_RCR1_RWDLEN1_16BIT /* RWDLEN1 = 2 Receive word length 1 bits, 16bit*/
- ),
- MCBSP_RCR2_RMK(
- MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 Receive phase number bit, single-phase frame*/
- MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
- MCBSP_RCR2_RWDLEN2_8BIT, /* RWDLEN2 = 0 */
- MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 receive companding mode bits, 0, no companding,MSB received first*/
- MCBSP_RCR2_RFIG_YES, /* RFIG = 0 Receive frame-sync ignore bit, 1, frame-sync detect */
- //MCBSP_RCR2_RDATDLY_1BIT /* RDATDLY = 1 Receive data delay bits, 1-bit data delay*/
- MCBSP_RCR2_RDATDLY_0BIT /* RDATDLY = 0 */
- ),
- MCBSP_XCR1_RMK(
- //MCBSP_XCR1_XFRLEN1_OF(1), /* XFRLEN1 = 1 Transmit frame length 1(1 to 128 words),Frame length=(XFRLEN1+1)words */
- MCBSP_XCR1_XFRLEN1_OF(0), /* XFRLEN1 = 0 */
- MCBSP_XCR1_XWDLEN1_16BIT /* XWDLEN1 = 2 Transmit word length 1.16bit*/
- ),
- MCBSP_XCR2_RMK(
- MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 Transmit phase number bit, single-phase frame*/
- MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
- MCBSP_XCR2_XWDLEN2_8BIT, /* XWDLEN2 = 0 */
- MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 Transmit companding mode bits, 0, no companding,MSB received first*/
- MCBSP_XCR2_XFIG_YES, /* XFIG = 0 Transmit frame-sync ignore bit, 1, frame-sync detect */
- //MCBSP_XCR2_XDATDLY_1BIT /* XDATDLY = 1 Transmit data delay bits, 1-bit data delay*/
- MCBSP_XCR2_XDATDLY_0BIT /* XDATDLY = 0 */
- ),
- //MCBSP_SRGR1_DEFAULT, /*(0x0001u)FWID=0,CLKGDV=1 */
- MCBSP_SRGR1_RMK(
- MCBSP_SRGR1_FWID_OF(1), /* FWID = 1 */
- MCBSP_SRGR1_CLKGDV_OF(1) /* CLKGDV = 1 */
- ),
- //MCBSP_SRGR2_DEFAULT, /*(0x2000u)CLKSM=1，Sample rate generator input clock mode bit */
- MCBSP_SRGR2_RMK(
- MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
- MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
- MCBSP_SRGR2_CLKSM_INTERNAL, /* CLKSM = 1 */
- MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */
- MCBSP_SRGR2_FPER_OF(15) /* FPER = 0 */
- ),
- MCBSP_MCR1_DEFAULT,
- MCBSP_MCR2_DEFAULT,
- MCBSP_PCR_RMK(
- MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 The McBSP remains active when the PERIPH domain is idled */
- MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 Transmit I/O enable bit, CLKX,FSX,DX,CLKS pins are serial port pins*/
- MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 Receive I/O enable bit, CLKR,FSR,DR,CLKS pins are serial port pins*/
- //MCBSP_PCR_FSXM_EXTERNAL, /* FSXM = 0 Transmit frame-sync mode bit,0:transmit fram-sync is supplied by an external source via the FSX pin*/
- MCBSP_PCR_FSXM_INTERNAL, /* FSXM = 1 */
- MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 Receive frame-sync mode bit,0:transmit fram-sync is supplied by an external source via the FSR pin*/
- 0, /* DXSTAT = N/A */
- //MCBSP_PCR_CLKXM_INPUT, /* CLKXM = 0 Transmit clock mode bit*/
- MCBSP_PCR_CLKXM_OUTPUT, /* CLKXM = 1 */
- MCBSP_PCR_CLKRM_INPUT, /* CLKRM = 0 Receive clock mode bit*/
- MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 Sample rate generator input clock mode bit,used with CLKSM to select the input clock*/
- MCBSP_PCR_FSXP_ACTIVEHIGH, /* FSXP = 0 Transmit frame-sync polarity bit, 0,transmit frame-sync pulses are active high*/
- MCBSP_PCR_FSRP_ACTIVEHIGH, /* FSRP = 1 Receive frame-sync polarity bit, 0,receive frame-sync pulses are active high*/
- //MCBSP_PCR_CLKXP_FALLING, /* CLKXP = 1 Transmit clock polarity bit,1,transmit data is driven on the rising edge of CLKX */
- MCBSP_PCR_CLKXP_RISING, /* CLKXP = 0 */
- //MCBSP_PCR_CLKRP_RISING /* CLKRP = 1 Receive clock polarity bit*/
- MCBSP_PCR_CLKRP_FALLING /* CLKRP = 0 */
- ),
- MCBSP_RCERA_DEFAULT,
- MCBSP_RCERB_DEFAULT,
- MCBSP_RCERC_DEFAULT,
- MCBSP_RCERD_DEFAULT,
- MCBSP_RCERE_DEFAULT,
- MCBSP_RCERF_DEFAULT,
- MCBSP_RCERG_DEFAULT,
- MCBSP_RCERH_DEFAULT,
- MCBSP_XCERA_DEFAULT,
- MCBSP_XCERB_DEFAULT,
- MCBSP_XCERC_DEFAULT,
- MCBSP_XCERD_DEFAULT,
- MCBSP_XCERE_DEFAULT,
- MCBSP_XCERF_DEFAULT,
- MCBSP_XCERG_DEFAULT,
- MCBSP_XCERH_DEFAULT
- };
楼主
