[STM32F1] STM32CubeMx生成FSMC工程驱动SSD1963+AT043TN25

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 楼主| sunwise123 发表于 2017-1-8 15:45 | 显示全部楼层 |阅读模式
关于STMCubeMx生成FSMC驱动,把相关配置参数贴上来。
1.pinout配置。LCD register select A0,是选择FSMC地址线A0作为SSD1963 寄存器/数据选择位(RS)。
2.时钟配置。
3.FSMC配置。

操作SSD1963实际上只操作两个16位大小的地址,一个当做命令寄存器来操作,一个当做数据缓存来操作。
(地址线A0为1时是写数据操作,A0为0时是写命令操作)
例如:
/* USER CODE BEGIN 0 */
#define LCD_REG (volatile uint16_t *)(0x6c000000)
#define LCD_RAM (volatile uint16_t *)(0x6c000002)


void LCD_WREG(uint16_t command)
{
    *LCD_REG = command;
}

void LCD_WRAM(uint16_t data)
{
    *LCD_RAM = data ;
}


相关概念:前廊,后廊
显示器的一帧由若干横行组成,比如AT043TN25是800*272的屏就是有272个横行。SSD1963上的驱动信号比272多几个,多的就是FP(前廊) 和BP(后廊)。
这两段时间内,显示数据是不会刷新到屏上的。
main.c中的一段代码如下:
#define SSD_HOR_RESOLUTION                800                //水平像素
#define SSD_VER_RESOLUTION                272                //垂直像素

#define SSD_HOR_BACK_PORCH                46                //水平后廊
#define SSD_HOR_FRONT_PORCH                210                //水平前廊

#define SSD_VER_BACK_PORCH                23                //垂直后廊
#define SSD_VER_FRONT_PORCH                22                //垂直前廊

#define SSD_HT        (SSD_HOR_RESOLUTION+SSD_HOR_BACK_PORCH+SSD_HOR_FRONT_PORCH)//显示+不显示
#define SSD_HPS        (SSD_HOR_BACK_PORCH)  //不显示
#define SSD_VT         (SSD_VER_RESOLUTION+SSD_VER_BACK_PORCH+SSD_VER_FRONT_PORCH)//显示+不显示
#define SSD_VPS (SSD_VER_BACK_PORCH)  //不显示


篇幅限制,部分main.c如下:
  1. /* USER CODE BEGIN 0 */
  2. #define LCD_REG (volatile uint16_t *)(0x6c000000)
  3. #define LCD_RAM (volatile uint16_t *)(0x6c000002)

  4. //LCD·Ö±æÂÊÉèÖÃ
  5. #define SSD_HOR_RESOLUTION                800                //LCDˮƽ·Ö±æÂÊ
  6. #define SSD_VER_RESOLUTION                272                //LCD´¹Ö±·Ö±æÂÊ

  7. #define SSD_HOR_PULSE_WIDTH                1                //ˮƽÂö¿í
  8. #define SSD_HOR_BACK_PORCH                46                //ˮƽǰÀÈ
  9. #define SSD_HOR_FRONT_PORCH                210                //ˮƽºóÀÈ

  10. #define SSD_VER_PULSE_WIDTH                1                //´¹Ö±Âö¿í
  11. #define SSD_VER_BACK_PORCH                23                //´¹Ö±Ç°ÀÈ
  12. #define SSD_VER_FRONT_PORCH                22                //´¹Ö±Ç°ÀÈ

  13. #define SSD_HT        (SSD_HOR_RESOLUTION+SSD_HOR_BACK_PORCH+SSD_HOR_FRONT_PORCH)//×ܵÄÖÜÆÚÊý£¬ÏÔʾµÄ+²»ÏÔʾµÄ
  14. #define SSD_HPS        (SSD_HOR_BACK_PORCH)  //²»ÏÔʾµÄ
  15. #define SSD_VT         (SSD_VER_RESOLUTION+SSD_VER_BACK_PORCH+SSD_VER_FRONT_PORCH)//×ܵÄÖÜÆÚÊý£¬ÏÔʾµÄ+²»ÏÔʾµÄ
  16. #define SSD_VPS (SSD_VER_BACK_PORCH)  //²»ÏÔʾµÄ

  17. //LCDÖØÒª²ÎÊý¼¯
  18. typedef struct
  19. {
  20.     uint16_t width;                          //LCD ¿í¶È
  21.     uint16_t height;                        //LCD ¸ß¶È
  22.     uint16_t ID;
  23.     uint8_t  dir;                            //ºáÆÁ»¹ÊÇÊúÆÁ¿ØÖÆ£º0£¬ÊúÆÁ£»1£¬ºáÆÁ¡£
  24.     uint16_t wramcmd;                  //¿ªÊ¼Ð´gramÖ¸Áî
  25.     uint16_t setxcmd;                  //ÉèÖÃx×ø±êÖ¸Áî
  26.     uint16_t setycmd;                  //ÉèÖÃy×ø±êÖ¸Áî
  27. } _lcd_dev;

  28. //LCD²ÎÊý
  29. _lcd_dev lcddev;        //¹ÜÀíLCDÖØÒª²ÎÊý
  30. uint16_t result;
  31. uint32_t i ;
  32. uint16_t color=0,pan=0;

  33. void LCD_WREG(uint16_t command)
  34. {
  35.     *LCD_REG = command;
  36. }

  37. void LCD_WRAM(uint16_t data)
  38. {

  39.     *LCD_RAM = data ;
  40. }

  41. uint16_t LCD_RRAM(void)
  42. {
  43.     uint16_t data;

  44.     data = *LCD_RAM;

  45.     return(data);
  46. }

  47. uint16_t LCD_Read_REG(uint16_t reg)
  48. {
  49.     uint16_t ram;

  50.     LCD_WREG(reg);
  51.     HAL_Delay(1);
  52.     ram = LCD_RRAM();

  53.     return(ram);
  54. }

  55. void SSD1963_43_Init(void)
  56. {
  57.     HAL_Delay(1);
  58.     LCD_WREG(0XA1);
  59.     result = LCD_RRAM();
  60.     result = LCD_RRAM();        //¶Á»Ø0X57
  61.     result <<= 8;
  62.     result |= LCD_RRAM();        //¶Á»Ø0X61
  63.     if(result == 0x5761)
  64.         result = 0x1963;
  65.     printf("ID = %x\n", result);
  66.     /*
  67.     set_pll_mn
  68.     Command 0xE2
  69.     Parameters 3
  70.     D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex
  71.     Command 0 1 1 1 0 0 0 1 0 E2
  72.     Parameter 1 1 M7 M6 M5 M4 M3 M2 M1 M0 xx
  73.     Parameter 2 1 0 0 0 0 N3 N2 N1 N0 xx
  74.     Parameter 3 1 0 0 0 0 0 C2 0 0 xx
  75.     Description
  76.     Set the MN of PLL
  77.     M[7:0] : Multiplier (M) of PLL. (POR = 00101101)
  78.     N[3:0] : Divider (N) of PLL. (POR = 0011)
  79.     C[2] : Effectuate MN value (POR = 0)
  80.     0 Ignore the multiplier (N) and divider (N) values
  81.     1 Effectuate the multiplier and divider value
  82.     VCO = Reference input clock x (M + 1)
  83.     PLL frequency = VCO / (N + 1)
  84.     * Note : 250MHz < VCO < 800MHz
  85.     For a 10MHz reference clock to obtain 100MHz PLL frequency, user cannot program M = 19 and N = 1. The setting in
  86.     this situation is setting M=29 and N=2, where 10 x 30 / 3 = 100MHz.
  87.     */
  88.     LCD_WREG(0xE2);                //Set PLL with OSC = 10MHz (hardware),        Multiplier N = 35, 250MHz < VCO < 800MHz = OSC*(N+1), VCO = 300MHz
  89.     LCD_WRAM(0x1D);                //²ÎÊý1 M=29
  90.     LCD_WRAM(0x02);                //²ÎÊý2 N=2
  91.     LCD_WRAM(0x04);                //²ÎÊý3 Ó¦ÓòÎÊý
  92.     printf("PLL frequency= 100M\n");
  93.     HAL_Delay(1);
  94.     /*
  95.     set_pll
  96.     Command 0xE0
  97.     Parameters 1
  98.     D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex
  99.     Command 0 1 1 1 0 0 0 0 0 E0
  100.     Parameter 1 1 0 0 0 0 0 0 A1 A0 xx
  101.     Description
  102.     Start the PLL. Before the start, the system was operated with the crystal oscillator or clock input.
  103.     A[1] : Lock PLL (POR = 0)
  104.     After PLL enabled for 100us, can start to lock PLL
  105.     0 Use reference clock as system clock
  106.     1 Use PLL output as system clock
  107.     A[0] : Enable PLL (POR = 0)
  108.     0 Disable PLL
  109.     1 Enable PLL
  110.     Before enabling PLL, the PLL setting (“0xE2”) have to be configured first. After PLL enabled for 100us, can start to
  111.     lock PLL. SSD1963 needed to switch to PLL output as system clock after PLL is locked. The following is the program
  112.     sequence.
  113.     WRITE COMMAND “0xE0”
  114.     WRITE DATA “0x01”
  115.     Wait 100us to let the PLL stable
  116.     WRITE COMMAND “0xE0”
  117.     WRITE DATA “0x03”
  118.     WRITE COMMAND “0x01”
  119.     * Note : SSD1963 is operating under reference clock before PLL is locked, registers cannot be set faster than half of the
  120.     reference clock frequency. For instance, SSD1963 with a 10MHz reference clock is not allowed to be programmed
  121.     higher than 5M words/s.
  122.     */
  123.     LCD_WREG(0xE0);                // Start PLL command
  124.     LCD_WRAM(0x01);                // enable PLL
  125.     HAL_Delay(1);
  126.     LCD_WREG(0xE0);                // Start PLL command again
  127.     LCD_WRAM(0x03);                // now, use PLL output as system clock
  128.     HAL_Delay(1);
  129.     LCD_WREG(0x01);                //Èí¸´Î»
  130.     HAL_Delay(1);
  131.     /*
  132.     set_lshift_freq
  133.     Command 0xE6
  134.     Parameters 3
  135.     D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex
  136.     Command 0 1 1 1 0 0 1 1 0 E6
  137.     Parameter 1 1 0 0 0 0 LCDC_FPR19 LCDC_FPR18 LCDC_FPR17 LCDC_FPR16 xx
  138.     Parameter 2 1 LCDC_FPR15 LCDC_FPR14 LCDC_FPR13 LCDC_FPR12 LCDC_FPR11 LCDC_FPR10 LCDC_FPR9 LCDC_FPR8 xx
  139.     Parameter 3 1 LCDC_FPR7 LCDC_FPR6 LCDC_FPR 5 LCDC_FPR4 LCDC_FPR 3 LCDC_FPR2 LCDC_FPR1 LCDC_FPR0 xx
  140.     Description
  141.     Set the LSHIFT (pixel clock) frequency
  142.     LCDC_FPR[19:16] : The highest 4 bits for the pixel clock frequency settings. (POR = 0111)
  143.     LCDC_FPR[15:8] : The higher byte for the pixel clock frequency settings. (POR = 11111111)
  144.     LCDC_FPR[7:0] : The low byte for the pixel clock frequency settings. (POR = 11111111)
  145.     For parallel LCD interface:
  146.     Configure the pixel clock to PLL freq x ((LCDC_FPR + 1) / 1048576)
  147.     To obtain PCLK = 5.3MHz with PLL Frequency = 100MHz,
  148.     5.3MHz = 100MHz * ( LCDC_FPR+ 1) / 1048576
  149.     LCDC_FPR = 55574
  150.     WRITE COMMAND “0xE6”
  151.     WRITE DATA “0x00” (LCDC_FPR = 55574)
  152.     WRITE DATA “0xD9”
  153.     WRITE DATA “0x16”
  154.     For serial LCD interface:
  155.     Configure the pixel clock to PLL freq x ((LCDC_FPR + 1) / 1048576) *4
  156.     To obtain PCLK = 5.3MHz with PLL Frequency = 100MHz,
  157.     5.3MHz = 100MHz * ( ( LCDC_FPR+ 1) / 1048576 )*4
  158.     LCDC_FPR = 13892
  159.     WRITE COMMAND “0xE6”
  160.     WRITE DATA “0x00” (LCDC_FPR = 13892)
  161.     WRITE DATA “0x36”
  162.     WRITE DATA “0x44”
  163.     */
  164.     LCD_WREG(0xE6);                //ÉèÖÃÏñËØÆµÂÊ,300Mhz
  165.     LCD_WRAM(0x2F);
  166.     LCD_WRAM(0xFF);
  167.     LCD_WRAM(0xFF);
  168.     /*
  169.     set_lcd_mode
  170.     Command 0xB0
  171.     Parameters 7
  172.     D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex
  173.     Command 0 1 0 1 1 0 0 0 0 B0
  174.     Parameter 1 1 0 0 A5 A4 A3 A2 A1 A0 xx
  175.     Parameter 2 1 0 B6 B5 0 0 0 0 0 xx
  176.     Parameter 3 1 0 0 0 0 0 HDP10 HDP9 HDP8 xx
  177.     Parameter 4 1 HDP7 HDP6 HDP5 HDP4 HDP3 HDP2 HDP1 HDP0 xx
  178.     Parameter 5 1 0 0 0 0 0 VDP10 VDP9 VDP8 xx
  179.     Parameter 6 1 VDP7 VDP6 VDP5 VDP4 VDP3 VDP2 VDP1 VDP0 xx
  180.     Parameter 7 1 0 0 G5 G4 G3 G2 G1 G0 xx
  181.     Description
  182.     Set the LCD panel mode and resolution
  183.     A[5] : TFT panel data width (POR = 0)
  184.     0 18-bit
  185.     1 24-bit
  186.     A[4] : TFT color depth enhancement enable (POR = 0)
  187.     0 Disable FRC or dithering
  188.     1 Enable FRC or dithering for color depth enhancement
  189.     If the panel data width was set to 24-bit,
  190.     FRC and dithering feature will be disabled automatic regardless the value of this register.
  191.     A[3] : TFT FRC enable (POR = 0)
  192.     0 TFT dithering enable
  193.     1 TFT FRC enableSSD1963 Rev 1.1 P 45/93 Jan 2010 Solomon Systech
  194.     A[5] A[4] A[3] TFT FRC TFT dithering
  195.     0 0 X Disable Disable
  196.     0 1 0 Disable Enable
  197.     0 1 1 Enable Disable
  198.     1 X X Disable Disable
  199.     A[2] : LSHIFT polarity (POR = 0)
  200.     Set the dot clock pulse polarity.
  201.     0 Data latch in falling edge
  202.     1 Data latch in rising edge
  203.     A[1] : LLINE polarity (POR = 0)
  204.     Set the horizontal sync pulse polarity.
  205.     0 Active low
  206.     1 Active high
  207.     A[0] : LFRAME polarity (POR = 0)
  208.     Set the vertical sync pulse polarity.
  209.     0 Active low
  210.     1 Active high
  211.     B[6:5] : TFT type (POR = 01)
  212.     00, 01 TFT mode
  213.     10 Serial RGB mode
  214.     11 Serial RGB+dummy mode
  215.     HDP [10:8] : High byte of the horizontal panel size (POR = 010)
  216.     HDP [7:0] : Low byte of the horizontal panel size (POR = 01111111)
  217.     Horizontal panel size = (HDP + 1) pixels
  218.     VDP [10:8] : High byte of the vertical panel size (POR = 001)
  219.     VDP [7:0] : Low byte of the vertical panel size (POR = 11011111)
  220.     Vertical panel size = (VDP + 1) lines
  221.     G[5:3] : Even line RGB sequence for serial TFT interface (POR = 000)
  222.     000 RGB
  223.     001 RBG
  224.     010 GRB
  225.     011 GBR
  226.     100 BRG
  227.     101 BGR
  228.     11x Reserved
  229.     G[2:0] : Odd line RGB sequence for serial TFT interface (POR = 000)
  230.     000 RGB
  231.     001 RBG
  232.     010 GRB
  233.     011 GBR
  234.     100 BRG
  235.     101 BGR
  236.     11x Reserved
  237.     */
  238.     LCD_WREG(0xB0);                //ÉèÖÃLCDģʽ
  239.     LCD_WRAM(0x20);                //24λģʽ
  240.     LCD_WRAM(0x00);                //TFT ģʽ

  241.     LCD_WRAM((SSD_HOR_RESOLUTION - 1) >> 8); //ÉèÖÃLCDˮƽÏñËØ
  242.     LCD_WRAM(SSD_HOR_RESOLUTION - 1);
  243.     LCD_WRAM((SSD_VER_RESOLUTION - 1) >> 8); //ÉèÖÃLCD´¹Ö±ÏñËØ
  244.     LCD_WRAM(SSD_VER_RESOLUTION - 1);
  245.     LCD_WRAM(0x00);                //RGBÐòÁÐ
  246.     printf("set_lcd_mode\n");
  247.     /*
  248.     set_hori_period
  249.     Command 0xB4
  250.     Parameters 8
  251.     D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex
  252.     Command 0 1 0 1 1 0 1 0 0 B4
  253.     Parameter 1 1 0 0 0 0 0 HT10 HT9 HT8 xx
  254.     Parameter 2 1 HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 xx
  255.     Parameter 3 1 0 0 0 0 0 HPS10 HPS9 HPS8 xx
  256.     Parameter 4 1 HPS7 HPS6 HPS5 HPS4 HPS3 HPS2 HPS1 HPS0 xx
  257.     Parameter 5 1 0 HPW6 HPW5 HPW4 HPW3 HPW2 HPW1 HPW0 xx
  258.     Parameter 6 1 0 0 0 0 0 LPS10 LPS9 LPS8 xx
  259.     Parameter 7 1 LPS7 LPS6 LPS5 LPS4 LPS3 LPS2 LPS1 LPS0 xx
  260.     Parameter 8 1 0 0 0 0 0 0 LPSPP1 LPSPP0 xx
  261.     Description
  262.     Set front porch and back porch
  263.     HT[10:8] : High byte of horizontal total period (display + non-display) in pixel clock (POR = 010)
  264.     HT[7:0] : Low byte of the horizontal total period (display + non-display) in pixel clock (POR = 10101111)
  265.     Horizontal total period = (HT + 1) pixels
  266.     HPS[10:8] : High byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first
  267.     display data. (POR = 000)
  268.     HPS[7:0] : Low byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first
  269.     display data. (POR = 00100000)
  270.     For TFT : Horizontal Sync Pulse Start Position = HPS pixels
  271.     For Serial TFT : Horizontal Sync Pulse Start Position = HPS pixels + LPSPP subpixels
  272.     HPW[6:0] : Set the horizontal sync pulse width (LLINE) in pixel clock. (POR = 0000111)
  273.     Horizontal Sync Pulse Width = (HPW + 1) pixelsSolomon Systech Jan 2010 P 48/93 Rev 1.1 SSD1963
  274.     LPS[10:8] : Set the horizontal sync pulse (LLINE) start location in pixel clock. (POR = 000)
  275.     LPS[7:0] : Set the horizontal sync pulse width (LLINE) in start. (POR = 00000000)
  276.     Horizontal Display Period Start Position = LPS pixels
  277.     LPSPP[1:0] : Set the horizontal sync pulse subpixel start position for serial TFT interface (POR = 00)
  278.     */
  279.     LCD_WREG(0xB4);                //Set horizontal period
  280.     LCD_WRAM((SSD_HT - 1) >> 8);
  281.     LCD_WRAM(SSD_HT - 1);
  282.     LCD_WRAM(SSD_HPS >> 8);
  283.     LCD_WRAM(SSD_HPS);
  284.     LCD_WRAM(SSD_HOR_PULSE_WIDTH - 1);
  285.     LCD_WRAM(0x00);
  286.     LCD_WRAM(0x00);
  287.     LCD_WRAM(0x00);
  288.     LCD_WREG(0xB6);                //Set vertical period
  289.     LCD_WRAM((SSD_VT - 1) >> 8);
  290.     LCD_WRAM(SSD_VT - 1);
  291.     LCD_WRAM(SSD_VPS >> 8);
  292.     LCD_WRAM(SSD_VPS);
  293.     LCD_WRAM(SSD_VER_FRONT_PORCH - 1);
  294.     LCD_WRAM(0x00);
  295.     LCD_WRAM(0x00);
  296.     printf("set_hori_period\n");
  297.     /*
  298.     set_pixel_data_interface
  299.     Command 0xF0
  300.     Parameters 1
  301.     D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex
  302.     Command 0 1 1 1 1 0 0 0 0 F0
  303.     Parameter 1 1 0 0 0 0 0 A2 A1 A0 xx
  304.     Description
  305.     Set the pixel data format to 8-bit / 9-bit / 12-bit / 16-bit / 16-bit(565) / 18-bit / 24-bit in the parallel host processor
  306.     interface. This command is used for display data only, the command format is always 8 bit.
  307.     A[2:0] : Pixel Data Interface Format (POR = 101)
  308.     000 8-bit
  309.     001 12-bit
  310.     010 16-bit packed
  311.     011 16-bit (565 format)
  312.     100 18-bit
  313.     101 24-bit
  314.     110 9-bit
  315.     Others Reserved
  316.     * Note : The un-used data bus will be driven to ground by SSD1963, so don’t connect the un-used data bus to
  317.     MCU
  318.     */
  319.     LCD_WREG(0xF0);        //ÉèÖÃSSD1963ÓëCPU½Ó¿ÚΪ16bit
  320.     LCD_WRAM(0x03);        //16-bit(565 format) data for 16bpp
  321.     printf("set_pixel_data_interface\n");
  322.     /*
  323.     set_display_on
  324.     Command 0x29
  325.     Parameters None
  326.     D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex
  327.     Command 0 0 0 1 0 1 0 0 1 29
  328.     Description
  329.     Show the image on the display panel
  330.     */
  331.     LCD_WREG(0x29);        //¿ªÆôÏÔʾ
  332.     printf("set_display_on\n");
  333.     /*


  334.     //ÉèÖÃPWMÊä³ö  ±³¹âͨ¹ýÕ¼¿Õ±È¿Éµ÷
  335.     LCD_WREG(0xD0);        //ÉèÖÃ×Ô¶¯°×ƽºâDBC
  336.     LCD_WRAM(0x00);        //disable

  337.     LCD_WREG(0xBE);        //ÅäÖÃPWMÊä³ö
  338.     LCD_WRAM(0x05);        //1ÉèÖÃPWMƵÂÊ
  339.     LCD_WRAM(0xFE);        //2ÉèÖÃPWMÕ¼¿Õ±È
  340.     LCD_WRAM(0x01);        //3ÉèÖÃC
  341.     LCD_WRAM(0x00);        //4ÉèÖÃD
  342.     LCD_WRAM(0x00);        //5ÉèÖÃE
  343.     LCD_WRAM(0x00);        //6ÉèÖÃF

  344.     LCD_WREG(0xB8);        //ÉèÖÃGPIOÅäÖÃ
  345.     LCD_WRAM(0x03);        //2¸öIO¿ÚÉèÖóÉÊä³ö
  346.     LCD_WRAM(0x01);        //GPIOʹÓÃÕý³£µÄIO¹¦ÄÜ
  347.     LCD_WREG(0xBA);
  348.     LCD_WRAM(0X01);        //GPIO[1:0]=01,¿ØÖÆLCD·½Ïò
  349.     */

  350.     LCD_WREG(0x36);        //ÉèÖÃɨÃèģʽ
  351.     LCD_WRAM(0x00);

  352. }
  353. /* USER CODE END 0 */

  354. int main(void)
  355. {

  356.     /* USER CODE BEGIN 1 */

  357.     /* USER CODE END 1 */

  358.     /* MCU Configuration----------------------------------------------------------*/

  359.     /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  360.     HAL_Init();

  361.     /* Configure the system clock */
  362.     SystemClock_Config();

  363.     /* Initialize all configured peripherals */
  364.     MX_GPIO_Init();
  365.     MX_FSMC_Init();

  366.     /* USER CODE BEGIN 2 */
  367.           SSD1963_43_Init();

  368.     printf("init end\n");
  369.     /* USER CODE END 2 */

  370.     /* Infinite loop */
  371.     /* USER CODE BEGIN WHILE */
  372.     while (1)
  373.     {
  374.         /* USER CODE END WHILE */

  375.         /* USER CODE BEGIN 3 */

  376.         lcddev.wramcmd = 0X2C;        //ÉèÖÃдÈëGRAMµÄÖ¸Áî
  377.         lcddev.setxcmd = 0X2A;        //ÉèÖÃдX×ø±êÖ¸Áî
  378.         lcddev.setycmd = 0X2B;        //ÉèÖÃдY×ø±êÖ¸Áî
  379.         lcddev.width = 800;                  //ÉèÖÿí¶È800
  380.         lcddev.height = 272;                //ÉèÖø߶È272

  381.         LCD_WREG(lcddev.setxcmd);//ÉèÖùâ±êλÖÃ
  382.         LCD_WRAM(0);
  383.         LCD_WRAM(0);
  384.         LCD_WRAM((lcddev.width - 1) >> 8);
  385.         LCD_WRAM((lcddev.width - 1) & 0XFF);

  386.         LCD_WREG(lcddev.setycmd);//ÉèÖùâ±êλÖÃ
  387.         LCD_WRAM(0);
  388.         LCD_WRAM(0);
  389.         LCD_WRAM((lcddev.height - 1) >> 8);
  390.         LCD_WRAM((lcddev.height - 1) & 0XFF);

  391.         LCD_WREG(lcddev.wramcmd);

  392.         color = 0;
  393.                                 pan = 0;

  394.         for(i = 0; i < (lcddev.width * lcddev.height); i++)
  395.         {
  396.                                         pan = pan & 0xFF;
  397.                                         pan ++;
  398.                                        
  399.                                         if(pan > 0xFF)
  400.                                         {
  401.                                                 color += 15;
  402.                                         }
  403.                                        
  404.           *LCD_RAM = color;
  405.         }

  406.         while(1);
  407.     }
  408.     /* USER CODE END 3 */

  409. }



测试打印结果如下:


Pinout配置

Pinout配置

时钟配置

时钟配置

FSMC配置

FSMC配置

打印结果

打印结果

实验结果

实验结果

SSD1963QL9.pdf

949.02 KB, 下载次数: 10

1963datasheet

AT043TN25 V2液晶屏.pdf

319.53 KB, 下载次数: 9

4.3寸液晶

dongnanxibei 发表于 2017-1-8 16:20 | 显示全部楼层
SD1963是晶门公司生产的一款TFT真彩色液晶屏显示控制器,内部集成有1215KB的帧缓冲器,支持864X480像素点的24位真彩色图片的显示。芯片支持不同总线宽度的微处理器并行接口用以接收来自微处理器的图片数据和命令。它与LCD显示器接口支持普通的无RAM的LCD的驱动,色彩深度达到每像素点24位。
玛尼玛尼哄 发表于 2017-1-8 19:00 | 显示全部楼层
图文并茂啊,一看就明白了。
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