本帖最后由 epsmc 于 2010-5-7 15:23 编辑
architecture a of counter is
begin
process(clk) ---div frequancy process
variable cnt1: integer ;
variable cnt2: integer;
begin
if clk'event and clk ='1' then
if(cnt1 >1) then
cnt1:=0;
if(cnt2>1) then
cnt2:=0;
clock <= not clock;
else
cnt2:= cnt2 +1;
end if;
else
cnt1:= cnt1 +1;
end if;
end if;
end process;
end a;
仿真时怎么是20分频呢？ |
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