DSP28335 ADC采集 DMA搬数据

#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File

#include "DSP2833x_Examples.h" // DSP2833x Examples Include File



// Determine when the shift to right justify the data takes place

// Only one of these should be defined as 1.

// The other two should be defined as 0.





// ADC start parameters

#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT

#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz

#endif

#if (CPU_FRQ_100MHZ)

#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz

#endif

#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/1 = 25.5MHz/(1) = 25.0 MHz

#define ADC_SHCLK 0xf // S/H width in ADC module periods = 2 ADC cycle









// Global variable for this example







#define CPU_FREQ 150E6

#define LSPCLK_FREQ CPU_FREQ/4

#define SCI_FREQ 115200

#define SCI_PRD (LSPCLK_FREQ/(SCI_FREQ*8))-1









#define BUF_SIZE 160 // Sample buffer size



// Global variable for this example

Uint16 j = 0,ADC_END = 0; // ADC finish flag







#pragma DATA_SECTION(ADC_Result,"DMARAML4");

volatile float ADC_Result[160];



#pragma DATA_SECTION(DMABuf1,"DMARAML4");

volatile Uint16 DMABuf1[160];



volatile Uint16 *DMADest;

volatile Uint16 *DMASource;

interrupt void local_DINTCH1_ISR(void);





main()

{

Uint16 i;



InitSysCtrl();



// InitSciGpio();



EALLOW;

SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK

EDIS;





DINT;



InitPieCtrl();



// Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000;

IFR = 0x0000;



InitPieVectTable();

EALLOW;

// PieVectTable.SCIRXINTA = &sciaRxFifoIsr;

PieVectTable.DINTCH1= &local_DINTCH1_ISR;

EDIS;





// PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block

//PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, int1

// IER = 0x100; // Enable CPU INT

IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1)

EnableInterrupts();









InitAdc(); // For this example, init the ADC









// Specific ADC setup for this example:

AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; // Sequential mode: Sample rate = 1/[(2+ACQ_PS)*ADC clock in ns]

// = 1/(3*40ns) =8.3MHz (for 150 MHz SYSCLKOUT)

// = 1/(3*80ns) =4.17MHz (for 100 MHz SYSCLKOUT)

// If Simultaneous mode enabled: Sample rate = 1/[(3+ACQ_PS)*ADC clock in ns]

AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;

AdcRegs.ADCTRL1.bit.CPS = 0; //

AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode

AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;

AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;

// AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run



// AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1; // Enable Sequencer override feature

AdcRegs.ADCCHSELSEQ1.all = 0x0; // Initialize all ADC channel selects to A0

AdcRegs.ADCCHSELSEQ2.all = 0x0; // Initialize all ADC channel selects to A0

AdcRegs.ADCCHSELSEQ3.all = 0x0; // Initialize all ADC channel selects to A0

AdcRegs.ADCCHSELSEQ4.all = 0x0; // Initialize all ADC channel selects to A0



AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 15; // convert and store in 8 results registers



AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1

//AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS)



// Assumes ePWM1 clock is already enabled in InitSysCtrl();

EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group

EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount

EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event

EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value

EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1









// Clear SampleTable

for (i=0; i<BUF_SIZE; i++)

{

DMABuf1[i] = 0x0000;

}





// Configure DMA Channel

DMADest = &DMABuf1[0]; //Point DMA destination to the beginning of the array

DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base

DMACH1AddrConfig(DMADest,DMASource);

DMACH1BurstConfig(15,1,10);

DMACH1TransferConfig(9,-15,(-150 + 1));

DMACH1WrapConfig(100,100,100,100); //Don't use wrap function

DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,SYNC_DISABLE,SYNC_SRC,

OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);





StartDMACH1();

EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start

















// Waiting ADC finish

while(!ADC_END);

// Translate DMABuf to ADC_Result

for (i=0; i<BUF_SIZE; i++)

{

ADC_Result[i] = (float)DMABuf1[i] * 3.0 / 4096.0;

}



for(;;);







}













// INT7.1

interrupt void local_DINTCH1_ISR(void) // DMA Channel 1

{



// To receive more interrupts from this PIE group, acknowledge this interrupt

PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;

ADC_END = 1;

}













//===========================================================================

// No more.

//===========================================================================