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默夏|  楼主 | 2017-4-11 10:19 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
TE, ck, TI, IO, se
:Place:645 - A clock IOB clock component is not placed at an optimal clock
   IOB site. The clock IOB component <clk> is placed at site <G21>. The clock IO
   site can use the fast path between the IO and the Clock buffer/GCLK if the
   IOB is placed in the master Clock IOB Site. If this sub optimal condition is
   acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
   in the .ucf file to demote this message to a WARNING and allow your design to
   continue. However, the use of this override is highly discouraged as it may
   lead to very poor timing results. It is recommended that this error condition
   be corrected in the design. A list of all the COMP.PINs used in this clock
   placement rule is listed below. These examples can be used directly in the
   .ucf file to override this clock rule.
   < NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >
请问这是什么错误啊??

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