Note: 1 These options should be used in accordance with the Flash memory access time. The wait
states represent the ratio of the SYSCLK (system clock) period to the Flash memory access
time:
zero wait state, if 0 < SYSCLK ≤ 24 MHz
one wait state, if 24 MHz < SYSCLK ≤ 48 MHz
two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
您说的是这个吧 这个是从0HZ到72MHZ需要2个等待状态次数 是上电FLASH初始化时候出现 之后IIC通讯应该不会有影响了吧
楼主
标题置顶
标题高亮
