本帖最后由 jlgcumt 于 2010-6-1 17:23 编辑
ISE帮助文档里的，感觉Floorplan area/IO/Logic-Post-synthesis可以完全替代Floorplan IO-Pre-Synthesis，不知道为什么又多了一个Floorplan IO-Pre-Synthesis。
Following are the most commonly used methods of entering constraints:
User constraints (UCF) file, using one of the following tools:
Constraints Editor
ISE Text Editor
Floorplan Editor or Pinout and Area Constraints Editor (PACE)
Note Each tool is supported for different devices. For details, see Help with Placement Constraints.
HDL source file using a text editor
Xilinx constraints (XCF) file using a text editor or Constraints Editor
Each method allows you to specify most constraints, but certain methods are recommended over others in different situations, as described in the following sections.
Note See the "Entry Strategies for Xilinx Constraints" chapter of the Constraints Guide for detailed information on all the constraint entry methods. See the "Xilinx Constraints" chapter for the entry methods supported for each constraint.
UCF File Constraints
UCF file constraints are used during the implementation process. You can enter timing, placement, and pinout constraints in the UCF file. Edit your UCF file using any of the following methods:
The following Project Navigator User Constraints processes automatically open the UCF file in the recommended constraints entry tool for the process:
Create Timing Constraints
Modify timing constraints in the Constraints Editor. For more information, see Creating Timing Constraints.
Floorplan IO - Pre-Synthesis
Modify pinout constraints in Floorplan Editor or PACE. For more information, see Floorplanning I/O – Pre-Synthesis.
Edit Constraints (Text)
Modify constraints in a text editor. This method is recommended for quick, minor modifications. For more information, see Creating and Editing Constraints in a Text Editor.
Floorplan Area / IO/ Logic - Post-Synthesis
Modify area constraints in Floorplan Editor or PACE. For more information, see Floorplanning a Design – Post-Synthesis.
Note This process is not supported for CPLDs.
In the Sources tab, double-click the UCF file to edit it in your preferred constraints entry tool. You can specify the default constraints entry tool in the Editor Options page of the Preferences dialog box.
Each constraints entry tool is recommended for different situations as follows:
Constraints Editor
Constraints Editor is the recommended tool for entering timing constraints in most situations. After synthesis, this tool lists all the elements and nets in the design. It allows you to group common elements and nets as well as specify constraints for specific nets. It is not necessary to know the Xilinx® constraint syntax, because the tool enters the appropriate constraints based on the feedback you provide. For more information about Constraints Editor, see the Constraints Editor Help.
Floorplan Editor or PACE
You can use Floorplan Editor or PACE either before or after synthesis. Using a drag-and-drop approach, you can enter placement constraints, including pinout constraints, logic placement, and area constraints. For details, see Placement Constraints Strategies using Floorplan Editor or Placement Constraints Strategies using PACE.
Note Each tool is supported for different devices. For details, see Help with Placement Constraints.
Text Editor
Hand editing the UCF is recommended for modifying design constraints to meet changing timing requirements and for creating multiple versions of the UCF file for testing how different constraints affect the design. You can specify your preferred text editor in the Editor Options page of the Preferences dialog box.
Note Names of objects in the design, such as net names, must exactly match the case of the name as it exists in the source design netlist, either uppercase or lowercase. Entering constraints in all uppercase is recommended, for example, LOC, RLOC, BLKNM.
Using Multiple UCF Files
You can assign multiple UCF files to a top level module in your design, enabling you to organize constraints. To do this, select the top module in the Sources tab, and choose either Add Source or New Source from the Project menu. Add or create the UCF file. The new UCF file appears in the Sources tab. When you implement your design, all constraints are applied.
HDL File Constraints
The VHDL and Verilog hardware description languages (HDLs) allow you to embed constraints in the design code at the highest level of abstraction. This method is recommended for constraints that define the desired result of the HDL (FSM_ENCODING, MULT_STYLE) or specific optimization (REGISTER_DUPLICATION, MAX_FANOUT). This method offers the following advantages:
Ability to retain constraints throughout the design flow
During synthesis, net names in the HDL code are commonly changed to a new name chosen by the synthesis tool. The new name may vary depending on the synthesis tool and may even vary across synthesis runs using the same synthesis tool. Specifying the timing of the net within the HDL code allows the constraint to be applied consistently throughout the design, regardless of the net names assigned by the synthesis tool.
Support for recursive structures
Recursive structures are commonly used to instantiate device-specific components based on design parameters. By defining a common timing constraint for each generated structure, constraint definitions are independent of the final design implementation.
Ease of maintenance for complex design constraints
The high-level, generic nature of HDL-defined timing constraints simplifies the overhead required to maintain complex design constraints.
Reuse
Entering constraints in the HDL allows you to reuse the constraints code in other designs.
XCF File Constraints
You can use the Xilinx constraints (XCF) file when using XST as your synthesis tool. This file is typically used for entering the following constraints:
Timing constraints for XST
Synthesis constraints (when you want to keep the constraints separate from the HDL file)
Although XST automatically optimizes the design for timing performance during synthesis, adding timing constraints specifically for synthesis may help improve performance. If you have the Write Timing Constraints option enabled, these timing constraints are also passed on to the ISE™ implementation tools. You can set Synthesis Options in the Process Properties dialog box.
Note See the "Design Constraints" chapter of the XST User Guide for more information on the use of constraints in the XCF file.
To create and modify the XCF file, you must use a text editor or Constraints Editor. To use the XCF constraints in your design, you must specify the XCF file using the following Synthesis Options in the Process Properties dialog box:
Synthesis Constraints File: Browse and select the XCF file.
Use Synthesis Constraints File: Make sure this option is selected.
Note To open the Process Properties dialog box, right-click the Synthesize-XST process, and select Properties. For more information, see Setting Process Properties. |
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