以下是ST OTG库里的一个函数，不知道红色的那两句在干什么
USB_OTG_Status USB_OTG_CoreInitDev (USB_OTG_CORE_DEVICE *pdev)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_ep_ctl_data depctl;
uint32_t i;
USB_OTG_dev_cfg_data dcfg;
USB_OTG_fifo_size_data nptxfifosize;
USB_OTG_fifo_size_data txfifosize;
USB_OTG_dev_in_ep_msk_data msk;
dcfg.d32 = 0;
/* Set device speed */
InitDevSpeed (pdev);
/* Restart the Phy Clock */
WRITE_REG32(pdev->regs.pcgcctl, 0);
/* Device configuration register */
dcfg.d32 = READ_REG32( &pdev->regs.dev_regs->dev_cfg);
dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
WRITE_REG32( &pdev->regs.dev_regs->dev_cfg, dcfg.d32 );
/* set Rx FIFO size */
WRITE_REG32( &pdev->regs.common_regs->rx_fifo_siz, 160/*pdev->cfgs->host_rx_fifo_size*/);
/* Non-periodic Tx FIFO */
nptxfifosize.b.depth = DEV_NP_TX_FIFO_SIZE;
nptxfifosize.b.startaddr = RX_FIFO_SIZE;
WRITE_REG32( &pdev->regs.common_regs->np_tx_fifo_siz, nptxfifosize.d32 );
txfifosize.b.depth = DEV_NP_TX_FIFO_SIZE;
WRITE_REG32( &pdev->regs.common_regs->dev_p_tx_fsiz_dieptxf[0], txfifosize.d32 );
txfifosize.b.startaddr += txfifosize.b.depth;
txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
/* Flush the FIFOs */
USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */
USB_OTG_FlushRxFifo(pdev);
/* Clear all pending Device Interrupts */
WRITE_REG32( &pdev->regs.dev_regs->dev_in_ep_msk, 0 );
WRITE_REG32( &pdev->regs.dev_regs->dev_out_ep_msk, 0 );
WRITE_REG32( &pdev->regs.dev_regs->dev_all_int, 0xFFFFFFFF );
WRITE_REG32( &pdev->regs.dev_regs->dev_all_int_msk, 0 );
for (i = 0; i <= MAX_TX_FIFOS; i++) //ha: SET OTG_FS_DIEPCTLx,OTG_FS_DIEPSIZEx,OTG_FS_DIEPINTx
{
depctl.d32 = READ_REG32(&pdev->regs.inep_regs->dev_in_ep_ctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
WRITE_REG32( &pdev->regs.inep_regs->dev_in_ep_ctl, depctl.d32);
WRITE_REG32( &pdev->regs.inep_regs->dev_in_ep_txfer_siz, 0);
WRITE_REG32( &pdev->regs.inep_regs->dev_in_ep_int, 0xFF);
}
for (i = 0; i < 1/* NUM_OUT_EPS*/; i++) //ha: SET OTG_FS_DOEPCTLx,OTG_FS_DOEPINTx,OTG_FS_DOEPTSIZx
{
USB_OTG_dev_ep_ctl_data depctl;
depctl.d32 = READ_REG32(&pdev->regs.outep_regs->dev_out_ep_ctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
WRITE_REG32( &pdev->regs.outep_regs->dev_out_ep_ctl, depctl.d32);
WRITE_REG32( &pdev->regs.outep_regs->dev_out_ep_txfer_siz, 0);
WRITE_REG32( &pdev->regs.outep_regs->dev_out_ep_int, 0xFF);
}
msk.d32 = 0;
msk.b.txfifoundrn = 1; //ha: OTG_FS_DIEPMSK
MODIFY_REG32(&pdev->regs.dev_regs->dev_in_ep_msk, msk.d32, msk.d32);
USB_OTG_EnableDevInt(pdev);
return status;
} |
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