打印
[Quartus]

Spartan-6 FPGA Configurable Logic Block

[复制链接]
1836|0
手机看帖
扫描二维码
随时随地手机跟帖
跳转到指定楼层
楼主
sherry88|  楼主 | 2010-8-25 10:09 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
Spartan-6 FPGA Configurable Logic Block
The Configurable Logic Blocks (CLBs) are the main logic resources for implementing sequential as well as combinatorial circuits. Each CLB element is connected to a switch matrix for access to the general routing matrix (shown in Figure 1). A CLB element contains a pair of slices. These two slices do not have direct connections to each other, and each slice is organized as a column. For each CLB, the slice in the bottom of the CLB is labeled as SLICE(0), and the slice in the top of the CLB is labeled as SLICE(1).

附件:请先登陆查看附件!

Spartan-6 FPGA Configurable Logic Block.rar (1.04 MB)

相关帖子

发新帖 我要提问
您需要登录后才可以回帖 登录 | 注册

本版积分规则

0

主题

91

帖子

1

粉丝