| Xilinx 培训资料2010之Virtex6- PCIe-Gen2 | Designing with the Virtex®-6 PCIe® Gen 2 Endpoint Block
1.Introduce engineers to the Xilinx® Virtex-6 integrated block for PCIe
2.Provide an overview of the Virtex-6 PCIe Gen 2 Endpoint Block design
and verification tools
3. At the end of the presentation, engineers will learn
– The basic architecture of the Virtex-6 integrated block for PCIe
– What Xilinx tools
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Virtex6_PCIe_Gen2_xfest_2009_v1_1.pdf
(1.41 MB)
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