本帖最后由 jujishoudong 于 2010-10-29 12:43 编辑
刚开始学Verilog，写的简单的一个testbench有错误，请教各位
`timescale 10ns/100ps
`include "and1.v"
and1 dd(a,b,c);
module tt;
reg clk,a,b;
output c;
initial
begin
clk=0;
a=1;
b=0;
end
always #10 clk=~clk;
[email=always@(posedge]always @(posedge[/email] clk)
begin
#2 a={$random}%2;
#10 b={$random}%2;
end
endmodule
错误提示：near "and1": syntax error, unexpected "IDENTIFIER", expecting "class" |
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