The watch dog timer is enabled by clearing the PORS bit in the CPU_SCR register. The watchdog timer is automatically set to three counts of sleep timer overflows. Once the watchdog timer is enabled it cannot be disabled. The only exception is when a PORS event takes place and the hardware writes ?1? to the PORS bit in the CPU_SCR register.
Watchdog can prevent the system from getting stalled in an infinite loop. A watchdog reset is generated when the watchdog timer reaches three. Firmware therefore must clear the watchdog timer periodically to avoid this reset. The firmware can clear the WDT, or both the WDT and the sleep timer by writing to the RES_WDT register. Any value can be written to clear the WDT (the erase is data independent). However to clear the sleep timer also, a value equal to 0x38 should be written by the firmware to the RES_WDT register.
RAM initializations can be disabled in a WDT reset. This is achieved by writing to IRAMDIS bit in the CPU_SCR1 register. In such a case, the SRAM contents are unaffected and the variables are alive during the reset.
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