ISE综合后PALCE&ROUTE
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <DEBUG_0_OBUF_BUFG> is placed at site <BUFGMUX_X2Y0>. The IO component <AC97Clk>
is placed at site <PAD184>. This will not allow the use of the fast path between the IO and the Clock buffer. If
this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the
.ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is
highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be
corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "AC97Clk" CLOCK_DEDICATED_ROUTE = FALSE; >
但板子做好了，不可能将它引到全局时钟脚上
在ucf里加上
NET "AC97Clk" CLOCK_DEDICATED_ROUTE = FALSE;
综合能通过
在ISE工程设计中，如果某个信号（如时钟信号AC97_CLK）是从非专用时钟引脚输入的，但在设计时又是作为时钟使用的，ISE布局布线时
也会自动将该信号作为全局时钟信号来布线，因其不是从全局时钟脚接入，故出现上述错误，无法布线成功。
如果不使用全局网络，这时可在约束文件（.ucf）中加上如下约束：
NET "AC97_CLK" CLOCK_DEDICATED_ROUTE=FLASE;
这样做是强制ISE不分配全局时钟网络给AC97_CLK，布线就能成功了。
那是不是说 非专用时钟引脚输入的信号不能做全局时钟来用？ |
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