....汗..应该是一个SCLK一个DIN输出.只是SCLK是反时钟而已.
写了简单的,你自己参考下吧.
entity clk_test is
port(
clk: in std_logic;
din_out : out std_logic_vector(0 to 1)
);
end clk_test;
architecture Behavioral of clk_test is
signal sclk :std_logic;
signal i : integer range 0 to 3;
signal c : integer range 0 to 4;
begin
din: process(sclk) is
begin
if sclk='0' and sclk'event then
case i is
when 0 =>din_out<="01";
when 1 =>din_out<="10";
when others => null;
end case;
i<=i+1;
end if;
if i=2 then
i<=0;
end if;
end process din;
clk1: process(clk) is
begin
if clk='1' and clk'event then
case c is
when 0 =>sclk<='0';
when 2 =>sclk<='1';
when 4 =>sclk<='0';
when others => null;
end case;
c<=c+1;
end if;
if c=4 then
c<=0;
end if;
end process clk1;
end Behavioral;
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