library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
------------------------------------------------------------------------------
entity c71_audio_frame_ind is
generic (threshold:natural);
port
(
rst : in std_logic;
clk : in std_logic;
dain : in std_logic;
frame_ind : out std_logic
);
end;
---------------------------------------------------------------------------
architecture bhv of c71_audio_frame_ind is
constant local_pn:std_logic_vector(63 downto 0):=B"1001011101010110100100111101100110111111000000100001100010100011";
subtype rega_wide is std_logic; subtype type的含义！！！
type rega_type is array(63 downto 0) of rega_wide;
subtype regb_wide is std_logic_vector(2 downto 0);
type regb_type is array(31 downto 0) of regb_wide;
subtype regc_wide is std_logic_vector(3 downto 0);
type regc_type is array(15 downto 0) of regc_wide;
subtype regd_wide is std_logic_vector(4 downto 0);
type regd_type is array(7 downto 0) of regd_wide;
subtype rege_wide is std_logic_vector(5 downto 0);
type rege_type is array(3 downto 0) of rege_wide;
subtype regf_wide is std_logic_vector(6 downto 0);
type regf_type is array(1 downto 0) of regf_wide;
signal da_shift : std_logic_vector(63 downto 0):=(others => '0');
signal shift_out : std_logic;
signal reg_a : rega_type;
signal reg_b : regb_type;
signal reg_c : regc_type;
signal reg_d : regd_type;
signal reg_e : rege_type;
signal reg_f : regf_type;
signal reg_g : std_logic_vector(7 downto 0):=(others => '0');
signal frame_ind_reg: std_logic;
signal mag_frame_reg: std_logic_vector(6 downto 0);
-----------------------------------------------------------------------------
begin
------------------------------------------------------------
--0.outputs mapping
frame_ind <= frame_ind_reg;
-----------------------------------------------------------
--1. to shiftregister the input data
shift_reg_p: process(rst,clk)
begin
if rst = '0' then
shift_out <= '0';
da_shift <= (others => '0');--x"0000000000000000";
elsif rising_edge(clk) then
shift_out <= da_shift(63);
da_shift(63 downto 1) <= da_shift(62 downto 0);
da_shift(0)<= dain;
end if;
end process;
----------------------------------------------------------
-- 2. to matched filtering the frame head
---2.1 to xor the input data with local_pn
match_1st_p:process(rst,clk,da_shift)
begin
if rst = '0' then
for i in 0 to 63 loop
reg_a(i) <= '0';
end loop;
elsif rising_edge(clk) then
for i in 63 downto 0 loop
reg_a(i) <= (local_pn(i) xor da_shift(i));
end loop;
end if;
end process;
---2.2 to summerize the xor results
sum_a_p:process(rst,clk,reg_a)
begin
if rst = '0' then
for i in 0 to 31 loop
reg_b(i) <= "000";
end loop;
elsif rising_edge(clk) then
for i in 0 to 31 loop
reg_b(i) <= ((reg_a(2*i)& reg_a(2*i)& '1')+(reg_a(2*i+1)& reg_a(2*i+1)& '1'));
end loop;
end if;
end process;
---2.3 to summerize the reg_b
sum_b_p:process(rst,clk,reg_b)
begin
if rst = '0' then
for i in 0 to 15 loop
reg_c(i) <= x"0";
end loop;
elsif rising_edge(clk) then
for i in 0 to 15 loop
reg_c(i) <= ((reg_b(2*i)(2)& reg_b(2*i))+(reg_b(2*i+1)(2)& reg_b(2*i+1)));
end loop;
end if;
end process;
---2.4 to summerize the reg_c
sum_c_p:process(rst,clk,reg_c)
begin
if rst = '0' then
for i in 0 to 7 loop
reg_d(i) <= ('0' & x"0");
end loop;
elsif rising_edge(clk) then
for i in 0 to 7 loop
reg_d(i) <= ((reg_c(2*i)(3)& reg_c(2*i))+(reg_c(2*i+1)(3)& reg_c(2*i+1)));
end loop;
end if;
end process;
---2.5 to summerize the reg_d
sum_d_p:process(rst,clk,reg_d)
begin
if rst = '0' then
for i in 0 to 3 loop
reg_e(i) <= ("00" & x"0");
end loop;
elsif rising_edge(clk) then
for i in 0 to 3 loop
reg_e(i) <= ((reg_d(2*i)(4)& reg_d(2*i))+(reg_d(2*i+1)(4)& reg_d(2*i+1)));
end loop;
end if;
end process;
---2.6 to summerize the reg_e
sum_e_p:process(rst,clk,reg_e)
begin
if rst = '0' then
for i in 0 to 1 loop
reg_f(i) <= ("000" & x"0");
end loop;
elsif rising_edge(clk) then
for i in 0 to 1 loop
reg_f(i) <= ((reg_e(2*i)(5)& reg_e(2*i))+(reg_e(2*i+1)(5)& reg_e(2*i+1)));
end loop;
end if;
end process;
---2.7 to summerize the reg_f
sum_f_p:process(rst,clk,reg_e)
begin
if rst = '0' then
reg_g <= x"00";
elsif rising_edge(clk) then
reg_g <= (reg_f(0)(6) & reg_f(0))+(reg_f(1)(6) & reg_f(1));
end if;
end process;
--------------------------------------------------------------------------------------------
--3. to calculate the abs of reg_g
abs_cal_p:process(rst,clk,reg_g)
begin
if rst = '0' then
mag_frame_reg <= "0000000";
elsif rising_edge(clk) then
if reg_g(7) = '1' then
mag_frame_reg <= not(reg_g(6 downto 0));
else
mag_frame_reg <= reg_g(6 downto 0);
end if;
end if;
end process;
--------------------------------------------------------------------------------------------
--4. to generate the frame_ind
frame_ind_reg <= '1' when (mag_frame_reg >= threshold) else
'0';
---------------------------------------------------------------------------------------------
end;
编译总是报错 就是can't determine definition of operator "+" |
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