PAGE WRITE
The IS24CXX is capable of page-WRITE (8-byte for 24C01/
02 and 16-byte for 24C04/08/16) operation. A page-WRITE
is initiated in the same manner as a byte write, but instead
of terminating the internal write cycle after the first data word
is transferred, the master device can transmit up to N more
bytes (N=7 for 24C01/02 and N=15 for 24C04/08/16). After
the receipt of each data word, the IS24CXX responds
immediately with an ACKnowledge on SDA line, and the
three lower (24C01/24C02) or four lower (24C04/24C08/
24C16) order data word address bits are internally
incremented by one, while the higher order bits of the data
word address remain constant. If the master device should
transmit more than N+1 (N=7 for 24C01/02 and N=15 for
24C04/08/16) words, prior to issuing the STOP condition,
the address counter will “roll over,” and the previously
written data will be overwritten. Once all N+1 (N=7 for
24C01/02 and N=15 for 24C04/08/16) bytes are received
and the STOP condition has been sent by the Master, the
internal programming cycle begins. At this point, all received
data is written to the IS24CXX in a single write cycle. All
inputs are disabled until completion of the internal WRITE
cycle.
以上的規格說24C01和24C02都是 0x07
雖然我取 0x03也行，但程序要進行換行，運行的時間比0x07長了點
EEPROM_24C01 EQU 0x03 ;4 bytes row structrue
EEPROM_24C01A EQU 0x07 ;8 bytes row structrue
EEPROM_24C02 EQU 0x07 ;8 bytes row structrue
EEPROM_24C04 EQU 0x0f ;16 bytes row structrue
EEPROM_24C08 EQU 0x0f ;16 bytes row structrue
EEPROM_24C16 EQU 0x0f ;16 bytes row structrue
;=========================================================================================
; EEPROMWrite
;=========================================================================================
EEPROMWrite:
ldi zI2CRepeat ,I2CFAILTIMES&0fh
?DeviceNoStabile:
ldi zI2CAck ,00h
sbim zI2CRepeat ,01h
baz Exit_EEPROMWrite
andim SDA_PINCR ,SDA^0x0f ;check bus
andim SCL_PINCR ,SCL^0x0f
nop
nop
nop
lda SDA_PIN ,0
sta zI2CAck ,0
andim zI2CAck ,SDA
baz ?DeviceIsBusy ;ready if sda pull high
lda SCL_PIN ,0
sta zI2CAck ,0
andim zI2CAck ,SCL
if SCL_PULL==SCL_PULLUP_TO_VDD
bnz ?DeviceIsReady ;if scl pull high
else
baz ?DeviceIsReady ;if scl pull down
endif
?DeviceIsBusy:
call IICStop
call Delay10ms
jmp ?DeviceNoStabile
?DeviceIsReady:
?EEPROMWriteOneByte:
call IICInit
;*** clear writeProtect
// andim WP_PIN ,WP^0x0f
call IICStart ;start
orim zI2CDevAddr ,DEV_WRITE ;write device addr
sta zI2CByteData+0 ,0
ldi zI2CByteData+1 ,DEV_COMMAND
call IICWriteByte
baz $+2
jmp ?DeviceIsBusy
lda zI2CByteAddr+0 ,0 ;write byte addr
sta zI2CByteData+0 ,0
lda zI2CByteAddr+1 ,0
sta zI2CByteData+1 ,0
call IICWriteByte
baz $+2
jmp ?DeviceIsBusy
?WriteUserData:
lda zI2CDPL ,0 ;prt->currentRAM
sta rzDPL ,0
lda zI2CDPM ,0
sta rzDPM ,0
lda zI2CDPH ,0
sta rzDPH ,0
lda rzINX ,0
sta zI2CByteData+0 ,0
adim rzDPL ,01h
eor rzDPL ,0
adcm rzDPM ,0
lda rzINX ,0
sta zI2CByteData+1 ,0
call IICWriteByte ;write one byte
baz ?successWrite
jmp ?DeviceIsBusy
?successWrite: ;if success,then
sbim zI2CCounter ,01h ;counter--
baz ?Finish_WriteEEPROM ;exit if counter=0
?syncUser:
adim zI2CDPL ,0x02 ;nextRAM <- ptr
eor zI2CDPL ,0
adcm zI2CDPM ,0
?syncDevice:
adim zI2CByteAddr+0 ,0x01
eor zI2CByteAddr+0 ,0
adcm zI2CByteAddr+1 ,0
or zI2CByteAddr+0 ,0
baz ?writeNextPage
;shift row meet 24C01 data structrue
ldi zWk0 ,EEPROM_24C01
and zI2CByteAddr+0 ,0
baz ?writeNextRow
?writeCurrentRow:
jmp ?WriteUserData
?writeNextPage:
adim zI2CDevAddr ,0x02
?writeNextRow:
andim zI2CDevAddr ,1110b
call IICStop
call Delay10ms ;continue to
jmp EEPROMWrite ;write next page
?Finish_WriteEEPROM:
call IICStop
call Delay10ms
ldi zI2CAck ,01h ;mark success flag
Exit_EEPROMWrite:
;*** set writeProtect
// orim WP_PIN ,WP
lda zI2CAck ,0
rtni ;to disable writing |
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