Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-Compatible Receiver
+3.3
V Analog Supply (VA)
+3.3
V Digital Supply (VD)
+3.3
V or +5.0
V Digital Interface Supply (VL)
8:2 S/PDIF Input MUX
AES/SPDIF Input Pins Selectable in Hardware
Mode
Three General Purpose Outputs (GPO) Allow
Signal Routing
Selectable Signal Routing to GPO Pins
S/PDIF-to-TX Inputs Selectable in Hardware
Mode
Flexible 3-wire Serial Digital Output Port
cirrus 8416 ms8416
Copyright
32
kHz to 192
kHz Sample Frequency Range
Lo-Jitter Clock Recovery
Pin and Microcontroller Read Access to
Channel Status and User Data
SPI™ or I²C
Control Port Software Mode and
Stand-Alone Hardware Mode
Differential Cable Receiver
On-Chip Channel Status Data Buffer Memories
Auto-Detection of Compressed Audio Input
Streams
Decodes CD Q Sub-Code
OMCK System Clock Mode
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