对C6747的PLL中SYSCLK1/2/4/6的分析
I 的“TMS320C6745/C6747DSPSystem Reference Guide”文档的P70页表述有误。
原文为“The divide values in PLL controller 0 for SYSCLK1/SYSCLK6, SYSCLK2, and SYSCLK4 are not fixed, so that you can change the divide values for power saving reasons. But you are responsible to assure that the divide ratios between these clock domains must be fixed to 1:2:4.”
其中红色的“divide ratios”应该改为“Divider Value”。
Divider Value = RATIO + 1.
我用SPI做的实验，当：
A: Uint8 PLLDIV1 = 1;
Uint8 PLLDIV2 = 3;
Uint8 PLLDIV4 = 7;
Uint8 PLLDIV6 = 1;
pllcRegs->PLLDIV1 = 0x8000 | PLLDIV1;
pllcRegs->PLLDIV2 = 0x8000 | PLLDIV2;
pllcRegs->PLLDIV4 = 0x8000 | PLLDIV4;
pllcRegs->PLLDIV6 = 0x8000 | PLLDIV6;
时发现，SPI master mode 下，SYSCLK2=300MHz/4=75MHz,故SPI主时钟为SYSCLK2/10=75MHz/10=7.5MHz。可以正常工作。
B: Uint8 PLLDIV1 = 2;
Uint8 PLLDIV2 = 4;
Uint8 PLLDIV4 = 6;
Uint8 PLLDIV6 = 8;
程序不能正常工作。而且SYSCLK1/SYSCLK6, SYSCLK2, and SYSCLK4要修改必须一起修改，不能只修改其中某一个参数。否则程序也不能正常工作。
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