Table of Contents
1.1 System-on-a-Reprogrammable Chip ....................................................................3
1.2 Why Use an FPGA?.............................................................................................4
1.2.1 ASIC vs. FPGA Design Flows .....................................................................4
1.3 A Common Design Reuse Strategy ......................................................................6
1.4 Definitions & Acronyms ......................................................................................7
2.1 System Synthesis and Timing Issues ....................................................................8
2.1.1 Synchronous vs. Asynchronous Design Style ...............................................8
2.1.3 System Clocking and Clock Distribution......................................................9
2.2 Memory and Memory Interface..........................................................................12
2.2.1 On-Chip Memory..........................................................................................12
2.2.2 Interfacing to Large Memory Blocks ..........................................................13
2.3 External Operability (I/O Standards) ..................................................................14
3.1 Abundance of Registers .....................................................................................16
3.1.1 Duplicating Registers .................................................................................16
3.1.2 Partitioning at Register Boundary...............................................................18
3.1.3 One-Hot State Machines.............................................................................18
3.1.4 Pipelining...................................................................................................18
3.2 Case and IF-Then-Else.......................................................................................20
3.3 Critical Path Optimization..................................................................................23
3.4 Tristate vs. Mux Buses.......................................................................................24
3.5 Arithmetic Functions..........................................................................................24
4.1 HDL Simulation and Testbench .........................................................................26
4.2 Static Timing .....................................................................................................26
4.3 Formal Verification............................................................................................27
1 Introduction......................................................................................... 3
2 System Level Reuse Issues for FPGAs ...............................................
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