#define CYGNUM_HAL_INTERRUPT_XTI_BASE 32
#define CYGNUM_HAL_INTERRUPT_SOFTWARE (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 0)
#define CYGNUM_HAL_INTERRUPT_USB_WAKEUP (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 1)
#define CYGNUM_HAL_INTERRUPT_PORT_2_8 (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 2)
#define CYGNUM_HAL_INTERRUPT_PORT_2_9 (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 3)
#define CYGNUM_HAL_INTERRUPT_PORT_2_10 (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 4)
....#define CYGNUM_HAL_INTERRUPT_PORT_1_13 (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 7)
#define CYGNUM_HAL_INTERRUPT_HCLK (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 7)
#define CYGNUM_HAL_INTERRUPT_I2C0_SCL (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 7)
#define CYGNUM_HAL_INTERRUPT_PORT_1_14 (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 8)
#define CYGNUM_HAL_INTERRUPT_HDRX (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 8)
#define CYGNUM_HAL_INTERRUPT_I2C0_SDA (CYGNUM_HAL_INTERRUPT_XTI_BASE+ 8)
....#define CYGNUM_HAL_INTERRUPT_PORT_0_2 (CYGNUM_HAL_INTERRUPT_XTI_BASE+10)
#define CYGNUM_HAL_INTERRUPT_SPI0_SCLK (CYGNUM_HAL_INTERRUPT_XTI_BASE+10)
#define CYGNUM_HAL_INTERRUPT_I2C1_SCL (CYGNUM_HAL_INTERRUPT_XTI_BASE+10)
#define CYGNUM_HAL_INTERRUPT_PORT_0_6 (CYGNUM_HAL_INTERRUPT_XTI_BASE+11)
#define CYGNUM_HAL_INTERRUPT_SPI1_SCLK (CYGNUM_HAL_INTERRUPT_XTI_B.......
#define CYGNUM_HAL_INTERRUPT_UART1_RX (CYGNUM_HAL_INTERRUPT_XTI_BASE+13)
#define CYGNUM_HAL_INTERRUPT_PORT_0_13 (CYGNUM_HAL_INTERRUPT_XTI_BASE+14)
#define CYGNUM_HAL_INTERRUPT_UART2_RX (CYGNUM_HAL_INTERRUPT_XTI_BASE+14)
#define CYGNUM_HAL_INTERRUPT_PORT_0_15 (CYGNUM_HAL_INTERRUPT_XTI_BASE+15)
#define CYGNUM_HAL_INTERRUPT_WAKEUP (CYGNUM_HAL_INTERRUPT_XTI_BASE+15)